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| 型號(hào)： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 43/140頁(yè) |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_revlog.fm.03
July 9, 2001
Revision Log
Page 129 of 131
Revision Log
Date
Description of Modification
August 8, 2000
Initial Release (Advance, IBM Confidential, Rev 0.7).
August 18, 2000
Minor corrections to signal names and addressing.
Development Release (Advance, IBM Confidential, Rev 0.8)
September 5, 2000
Added Clocking and Reset chapter.
Added Register Summary table to Configuration Registers chapter.
September 8, 2000
Moved JTAG chapter to after Pin Assignment chapter.
Added definition of reserved bits in Preface, page 13.
Revised section numbering throughout Configuration Registers chapter.
Added definition of discard timer in 5.2.5.10, page 77.
Numerous minor corrections to bit definitions throughout Configuration Registers chapter.
Revised Package Mechanical diagram, page 121.
Development Release (Advance, IBM Confidential, Rev 0.9)
September 19, 2000
Revised synchronous operation mode bullet in 2.1 Features list to also indicate asynchronous operation.
Revised Figure 6.1 to change kW to k
W.
Release to web (Advance, IBM Confidential, Rev 0.9)
November 14, 2000
Added detail to Chapters 9 and 10; minor corrections elsewhere.
Changed “Secondary Bus Memory” registers to “Opaque Memory” registers.
Added more detail to hot-plug description in Chapter 6.
Release to web developers site (Preliminary, IBM Confidential, Document Rev 00)
December 15, 2000
Added new register (Secondary Bus Private Device Mask Register) in Chapter 5.
Updated reset value of Opaque register, minor corrections to existing registers.
Changed three reserved pins to new signals, tables 14, 17, and 18 updated.
Release to web developers site (Preliminary, IBM Confidential, Document Rev 01)
April 6, 2001
Changed Reset Value in
Device ID Register on page 112 to x‘1494 0049’.
Changed description area in
Power and Ground Connections on page 101 in Table 16, for Input Name P_VDDA
and S_VDDA and added a note.
Changed Table 19 of
Power and Ground Connections on page 101, in bit rows 94,101, and 105.
Corrected field name and description area for masking of devices 14 and 15 in
Development Release (Preliminary, IBM Confidential, Rev1.1)
May 16, 2001
Added bullet to Optional Features, p. 7.
May 22, 2001
Section 2.1, Features - Added compliance statement for
PCI-X Addendum to the PCI Local Bus specification,
Revision 1.0a, July 24, 2000.
Added note to Table 15, pp. 100-101.
General Release version (rev 02).
May 23, 2001
Sections 5.2.5.1 and 5.2.5.2 Primary and Secondary Data Buffering Control Registers. Revised descriptions of
Bit 11 (Enable Relaxed Ordering).
Sections 5.2.5.21 and 5.2.5.22 Secondary Bus Upstream and Primary Bus Downstream Split Transaction Regis-
ters. Revised register descriptions.
June 8, 2001
Corrected inconsistencies in Revision Log.
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