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參數(shù)資料
| 型號： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 57/140頁 |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_operations.fm.03
July 9, 2001
Bus Operation
Page 15 of 131
3.2 Write Transactions
Write transactions are treated as either posted write or delayed/split (PCI-X) write transactions.
Table 3: Write Transaction Handling on page 15 shows how each type of write operation is handled by the
IBM 133 PCI-X Bridge R1.1.
3.2.1 Posted Write Transactions
Posted write forwarding is the default used for memory write and memory write and invalidate transactions.
Memory write block also uses write posting and is the only mode used for this command.
When the IBM 133 PCI-X Bridge R1.1 determines that a memory write transaction is to be forwarded across
the bridge, it first checks for empty space in the posted write buffer. If space is available in the posted write
buffer, the bridge accepts data until the buffer is full or the transaction is terminated. If the transaction is termi-
nated because of a buffer-full condition, the termination point is a 128-byte boundary. If there is no space in
the posted write buffer, the transaction is terminated with retry.
Up to eight posted write transactions can be enqueued on the bridge at any one time.
3.2.1.1 PCI to PCI-X Transactions
When the source bus is operating in conventional PCI mode and the destination bus is operating in PCI-X
mode, the bridge must buffer memory write transactions from the conventional PCI interface and count the
number of bytes to be forwarded to the PCI-X interface. If the conventional PCI transaction uses the memory
write command and some byte enables are deasserted, the bridge must use the PCI-X memory write
command. If the conventional PCI command is memory write and all byte enables are asserted, the bridge
will use the memory write PCI-X command. If the conventional transaction uses the memory write and invali-
date command, the bridge uses the PCI-X memory write block command.
The bridge attempts to transfer the write data on the PCI-X interface as soon as the transaction ends or a
128-byte boundary is crossed, whichever comes first. Writes of greater than 128 bytes are possible only if
more than one 128-byte sector fills up before the write operation is issued on the PCI-X interface.
3.2.1.2 PCI-X to PCI Transactions
When the source bus is operating in PCI-X mode and the destination bus is operating in conventional PCI
mode, the bridge uses the conventional memory write command for both the PCI-X memory write and PCI-X
memory write block commands.
Table 3: Write Transaction Handling
Type of Transaction
Type of Handling
Memory Write
Posted
Memory Write and Invalidate
Posted
Memory Write Block (PCI-X)
Posted
I/O Write
Delayed/Split (PCI-X)
Type 0 Configuration Write
Immediate
Type 1 Configuration Write
Delayed/Split (PCI-X)
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