參數(shù)資料
型號: IBM21P100BGB
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA304
封裝: 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304
文件頁數(shù): 85/140頁
文件大?。?/td> 2032K
代理商: IBM21P100BGB
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_pcix_regs.fm.03
July 9, 2001
Configuration Registers
Page 41 of 131
5.2.4.8 Latency Timer Register
This register specifies, in PCI bus clock units, the value of the Latency Timer for this device as a bus master.
Masters that can burst for more than two data phases must implement this register as Read/Write.
5.2.4.9 Header Type Register
This read only register specifies that a type x‘01’ header is being used for this device.
Address Offset
x‘0D’
Access
See individual fields
Reset Value
x'00' in PCI mode, x'40' in PCI-X mode
Primary Latency Timer
7654
3210
Bit(s)
Access
Field Name and Description
7:3
RW
Read/Write to set granularity in 8-cycle increments.
2:0
RO
Set to b‘000’ to force 8-cycle increments for the latency timer.
Address Offset
x‘0E’
Access
Read only
Reset Value
x‘01’
Header Type
7654
3210
Bit(s)
Access
Field Name and Description
7:0
RO
x‘01’
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