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| 型號(hào)： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 12/140頁(yè) |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_signals.fm.03
July 9, 2001
Signal Descriptions
Page 101 of 131
7.5 Power and Ground Connections
T_MODECTL
I
1
Driver Mode Control
Used to control the PCI/PCI-X driver impedance during manufacturing test. It should be
tied low for normal system operation.
T_RI#
I
1
Receiver Inhibit
Used to gate all receivers during manufacturing test. It must be tied high for normal sys-
tem operation.
TEST_CE0
I
1
Test Mode Enable
Used to enable scan testing of the bridge device during manufacturing test. It must be
tied low for normal system operation.
XCLK_OUT
O
1
PLL Output Monitor
This signal may be used to monitor the output of the phase-locked loop circuits for the
primary and secondary interfaces. During normal system operation, this output is in
high-impedance state and should be pulled down on the board.
Total
11
Table 16: List of Power and Ground Connections
Input Name
Number
Description
See
Note
P_VDDA
1
Quiet 2.5 V power supply connection to the PLL for the primary clock domain.
S_VDDA
1
Quiet 2.5 V power supply connection to the PLL for the secondary clock
domain.
VDD
16
2.5 V power supply connections for the internal logic.
VDD2
26
3.3 V power supply connections for the I/O circuits.
GND
48
Ground connections.
Total
92
1. A filtering circuit may be required to ensure a quiet supply at this pin (only if the asssociated bus is operated in PCI-X mode). A
suggested filtering circuit can be found in the “Phase-Locked Loop” chapter of the IBM “ASIC SA-12E Databook”.
Table 15: List of Test Signals (Page 2 of 2)
Signal Name
I/O
Width
Description
Note: With the bridge containing internal pull-up resistors on TDI, TMS, TRST#, and TCK, system designers need to assure voltage
dividers are not generated by the possible implementation of pull-down resistors as defined in sections 4.3.3 and 4.4.1 of the PCI 2.2
specification.
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