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| 型號(hào)： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 10/140頁(yè) |
| 文件大小： | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_signals.fm.03
July 9, 2001
Signal Descriptions
Page 99 of 131
7.3 Strapping Pins and Other Signals
Table 14: List of Strapping Pins and Other Signals (Page 1 of 2)
Signal Name
I/O
Width
Description
64_BIT_DEVICE#
I
1
Physical bus width of PCI-X device
Used only when the IBM 133 PCI-X Bridge R1.1 is employed as the bus interface on a
PCI-X add-in card. The PCI-X Specification requires that such devices indicate the phys-
ical width of their bus in bit 16 of the PCI-X Bridge Status register. Bit 16 of the PCI-X
Bridge Status register is set directly from the inverse of the 64_BIT_DEVICE# pin. This
information is used solely by configuration software; operation of the IBM 133 PCI-X
Bridge R1.1 is unaffected.
0
bit 16 of the PCI-X Bridge Status register is set to b’1’, indicating a 64 bit bus.
1
bit 16 of the PCI-X Bridge Status register is set to b’0’, indicating a 32 bit bus.
IDSEL_REROUTE_EN
I
1
IDSEL Reroute Enable
Used to enable the IDSEL reroute function at reset or power up. The reset value of the
Secondary Bus Private Device Mask register is modified according to the tie value of the
IDSEL_REROUTE_EN pin. Note that configuration software can subsequently modify
the Secondary Bus Private Device Mask register, regardless of how the
IDSEL_REROUTE_EN pin is tied.
0
reset value of Secondary Bus Private Device Mask register is x’00000000’.
1
reset value of Secondary Bus Private Device Mask register is x’22F20000’.
OPAQUE_EN
I
1
Opaque Region Enable
Used to enable the Opaque Memory Region at reset or power up. The reset value of Bit
0 of the Opaque Memory Enable register is modified according to the tie value of the
OPAQUE_EN pin. Note that configuration software can subsequently modify Bit 0 of the
Opaque Memory Enable register, regardless of how the OPAQUE_EN pin is tied.
0
reset value of bit 0 of Opaque Memory Enable register is b’0’.
1
reset value of bit 0 of Opaque Memory Enable register is b’1’.
P_DRVR_MODE
I
1
Primary driver mode control
Used to alter the output impedance of the primary bus PCI/PCI-X drivers, to account for
how many drops are on the bus. This line should be pulled through a resistor to a 0 or 1
as needed.
0
use default impedance value
1
select alternate impedance value
RESERVED
7
Reserved pins
RESERVED 1 and 2 should be left open and not connected. RESERVED 3-7 should be
pulled to ground.
S_DRVR_MODE
I
1
Secondary driver mode control
Used to alter the output impedance of the secondary bus PCI/PCI-X drivers, to account
for how many drops are on the bus. This line should be pulled through a resistor to a 0 or
1 as needed.
0
use default impedance value
1
select alternate impedance value
S_CLK_STABLE
I
1
S_CLK Input Stable
Indicates when the S_CLK input to the bridge is stable. It is used to determine when the
S_RST# signal may be deasserted.
0
S_CLK input is not yet stable
1
S_CLK input is stable
S_INT_ARB_EN#
I
1
Internal Arbiter Enable
Used to choose between the internal arbiter and external arbiter for the secondary bus.
0
Use internal arbiter
1
Disable internal arbiter, use external arbiter
Note: Each strapping pin or reserved pin should have an unshared series resistor tying it to either ground or 3.3 V. The value of the
resistor may be selected to limit part number count, but the value should be greater than or equal to 100 Ohms and less than or equal to
5000 Ohms.
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