IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_pcix_regs.fm.03
July 9, 2001
Configuration Registers
Page 85 of 131
5.2.5.29 Secondary Bus Private Device Mask Register
The Secondary Bus Private Device Mask register provides a means to implement private devices on the
secondary PCI bus. The process of converting Type 1 configuration transactions to Type 0 configuration
transactions is modified by the contents of this register. A configuration transaction that targets a device
masked by this register is rerouted to device 15. Setting the Secondary Bus Private Device Mask register to
zeros effectively disables this function.
Address Offset
x‘B0’
Access
R/W
Reset Value
x‘0000 0000’ When IDSEL_REROUTE_EN (AC22) is tied low. See
strapping considerations.
Reset Value
x‘22F2 0000’ When IDSEL_REROUTE_EN (AC22) is tied high. See
strapping considerations.
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3
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9
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
98
76543210
Bit(s)
Access
Field Name and Description
31:30
RW
Reserved
Masking for devices14 and 15 is not implemented. Operation of the IBM 133 PCI-X Bridge R1.1 is unaffected
by the value of these bits.
29
RW
Private Device Mask 13
0
Rerouting disabled for device 13
1
Block assertion of S_AD(29) for configuration transactions to device 13, assert S_AD(31) instead
28:26
RW
Reserved
Masking for devices 12, 11, and 10 is not implemented. Operation of the IBM 133 PCI-X Bridge R1.1 is unaf-
fected by the value of these bits.
25
RW
Private Device Mask 9
0
Rerouting disabled for device 9
1
Block assertion of S_AD(25) for configuration transactions to device 9, assert S_AD(31) instead
24
RW
Reserved
Masking for devices 8 is not implemented. Operation of the IBM 133 PCI-X Bridge R1.1 is unaffected by the
value of this bit.
23
RW
Private Device Mask 7
0
Rerouting disabled for device 7
1
Block assertion of S_AD(23) for configuration transactions to device 7, assert S_AD(31) instead