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參數(shù)資料
| 型號： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 60/140頁 |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Bus Operation
Page 18 of 131
ppb11_operations.fm.03
July 9, 2001
The bridge translates a PCI-X memory read block command into one of three conventional PCI memory read
commands based on the byte count and starting address. If the starting address and byte count are such that
only a single DWord (or less) is being read, the conventional transaction uses the memory read command. If
the PCI-X transaction reads more than one DWord, but does not cross a cache line boundary (as indicated by
the Cache Line Size register in the conventional Configuration Space header), the conventional transaction
uses the memory read line command. If the PCI-X transaction crosses a cache line boundary, the conven-
tional transaction uses the memory read multiple command.
If a disconnect occurs before the byte count of the PCI-X memory read block command is exhausted, the
bridge keeps issuing the command until all the bytes in the count are received. The bridge disconnects once
the buffer is filled and prefetches more data as 128-byte sectors of the buffer become free when split comple-
tion data is returned to the originator, until the byte count is exhausted.
3.3.1.3 PCI to PCI Transactions
This mode does not involve any translation.
If the Memory Read command targets non-prefetchable memory space, the memory read fetches only the
requested double word. Bits 9:8 of the Primary and Secondary Data Buffering Control registers control the
prefetching algorithm for the Memory Read command in prefetchable space. The default value of these bits
indicates that up to one cache line will be prefetched.
For the memory read line command, the prefetching algorithm is controlled by bits 7:6 of the Primary and
Secondary Data Buffering Control registers. The default value of these bits indicates that up to one cache line
will be prefetched.
For the memory read multiple command, the prefetching algorithm is controlled by bits 5:4 of the Primary and
Secondary Data Buffering Control registers. The default value of these bits indicates that a full prefetch will be
done, subject to the limit imposed by the maximum memory read byte count value set by bits (14:12) of the
same register. The default value is 512 bytes or an entire read buffer. Data fetching operations will be discon-
nected at all 1 MB boundaries.
3.3.1.4 PCI-X to PCI-X Transactions
This mode does not involve any translation.
The amount of data that is fetched is controlled by the Downstream and Upstream Split Transaction Control
register. The Split Transaction Capacity and Split Transaction Commitment Limit fields control how much
data is requested at any one time.
3.3.2 I/O Read
The I/O Read command is not translated and fetches a DWord of data. The command will either be split in
PCI-X mode or delayed in conventional PCI mode.
3.3.3 Configuration Read
3.3.3.1 Type 1 Configuration Read
The Type 1 configuration read command is only accepted on the primary interface. The command will either
be split in PCI-X mode or delayed in conventional PCI mode.
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