參數(shù)資料
型號： IBM21P100BGB
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304
文件頁數(shù)： 102/140頁
文件大?。?/td> 2032K
代理商： IBM21P100BGB
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Configuration Registers
Page 56 of 131
ppb11_pcix_regs.fm.03
July 9, 2001
5.2.5 Device-Specific Configuration Space Registers
The following sections are register by register descriptions of the Device-Specific Configuration Space
Region.
5.2.5.1 Primary Data Buffering Control Register
The Primary Data Buffering Control register provides controls for memory read transactions that are initiated
on the primary interface.
Address Offset
x‘40’
Access
See individual bit fields.
Reset Value
x‘0020’
Res
e
rv
ed
M
a
ximum
M
emor
y
R
e
a
d
B
yt
e
C
ount
E
n
a
b
le
Relax
e
d
O
rdering
Pr
im
ary
S
p
e
cial
Delayed
R
ead
Mode
Pr
im
ary
R
ead
Pref
et
ch
bit
s
Pr
im
ary
R
ead
Line
P
ref
et
ch
bit
s
Pr
im
ary
R
ead
Mult
ip
le
Pre
fet
ch
bi
ts
Reserved
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
15
RO
Reserved
14:12
RW
Maximum Memory Read Byte Count
These bits set the maximum byte count used by the bridge when generating read requests on the secondary
bus in response to a memory read operation initiated on the primary bus (when the primary bus is in PCI
mode). Device drivers must not modify these bits without considering the impact on the rest of the system.
These bits only have an effect if the prefetch mode bits for the PCI read command in use (bits (9:8), (7:6), or
(5:4) below) are set to “full prefetch”. The most recent value of this register is used each time the bridge makes
a new read request. The bits have the following meaning:
000
default to 512 bytes
001
128 bytes
010
256 bytes
011
512 bytes
100
1024 bytes
101
2048 bytes
110
4096 bytes
111
default to 512 bytes
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