參數(shù)資料
型號: IBM21P100BGB
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA304
封裝: 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304
文件頁數(shù): 106/140頁
文件大小: 2032K
代理商: IBM21P100BGB
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Configuration Registers
Page 60 of 131
ppb11_pcix_regs.fm.03
July 9, 2001
5.2.5.3 Miscellaneous Control Register
The Miscellaneous Control register provides controls for miscellaneous functions, such as handling parity
errors, in the bridge.
Address Offset
x‘44’
Access
Read/Write
Reset Value
x‘03’
Res
e
rv
ed
Dat
a
Parit
y
Error
R
ec
overy
E
nabl
e
Parit
y
E
rror
B
eha
vior
7654321
0
Bit(s)
Access
Field Name and Description
7:2
RO
Reserved
1RW
Data Parity Error Recovery Enable
0
Allow the bridge to pass parity errors through the bridge.
1
Cause SERR# to be asserted whenever either Master Data Parity Error bit (bit 8 in either the Status or
the Secondary Status register) is set.
The default value after reset is b‘1’.
0RW
Parity Error Behavior
This bit defines the bridge’s behavior when detecting a data parity error on a non-posted write transaction.
0
The bridge will pass the corrupted data sequence, PERR# will be asserted (if enabled), but the bridge
will not compare the data and BE# for performing completion on the initiating bus.
1
The transaction will be completed on the originating bus, PERR# will be asserted (if enabled), the
appropriate status bits will be set, the data will be discarded and no request will be enqueued.
The default value after reset is b‘1’.
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