參數(shù)資料
型號(hào)： IBM21P100BGB
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304
文件頁數(shù)： 79/140頁
文件大?。?/td> 2032K
代理商： IBM21P100BGB
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_pcix_regs.fm.03
July 9, 2001
Configuration Registers
Page 35 of 131
5.2.4.3 Command Register
This register provides a variety of configurable parameters defining the device’s interaction with the PCI bus.
Address Offset
x‘04’
Access
See individual bit fields.
Reset Value
x‘0000’
Reserved
F
a
st
B
a
ck
-t
o
-B
a
ck
C
o
n
tr
o
l
Sys
tem
E
rror
C
ont
rol
W
a
it
C
ycl
e
C
ont
ro
l
Parit
y
Error
R
es
ponse
VG
A
P
alet
te
Snoop
Cont
rol
Mem
o
ry
W
rit
e
and
In
validat
e
C
ont
rol
Spec
ia
l
C
ycles
Cont
rol
Bus
M
ast
e
r
C
ont
rol
Mem
o
ry
Spac
e
C
ont
rol
I/
O
S
pace
C
ont
rol
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
15:10
RO
Reserved
9RO
Fast Back-to-Back Control
0
Fast back-to-back transactions are allowed only for the same agent
This bit is ignored in PCI-X mode
8RW
System Error Control
0
Disable the SERR# output driver
1
Enable the SERR# output driver
7RO
Wait Cycle Control
0
Disable Address/Data stepping
This bit is ignored in PCI-X mode.
6RW
Parity Error Response
0
Ignore detected parity errors
1
Respond to detected parity errors
Controls the response to address and data parity errors on the primary interface. If this bit is set, the bridge
must take its normal action when a parity error is detected. If this bit is cleared, the bridge must ignore any par-
ity errors that it detects and continue normal operation. In either case, the parity error detected bit of the Status
register gets set if an address or data parity error is detected.
5RW
VGA Palette Snoop Control
0
Disable palette snooping; that is, treat palette accesses like all other accesses
1
Enable palette snooping
4RO
Memory Write and Invalidate Control
0
Disable MWI
This bit is ignored in PCI-X mode.
3RO
Special Cycles Control
0
Ignore special cycle operations
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