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| 型號(hào)： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 136/140頁(yè) |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_clock_reset.fm.03
July 9, 2001
Clocking and Reset
Page 87 of 131
6. Clocking and Reset
This section explains the clocking requirements and reset functions of the IBM 133 PCI-X Bridge R1.1.
6.1 Clocking Domains
The IBM 133 PCI-X Bridge R1.1 has two clocking domains: one for the primary interface, the other for the
secondary interface. Each interface has its own clock input pin: the primary interface is controlled by the
P_CLK input, and the secondary interface and the internal arbiter is controlled by the S_CLK input. Note that
the bridge does not supply clocks on either interface. The two bus clocks may be run synchronously or asyn-
chronously to one another. The two clock frequencies are independent of each other and each may have any
value allowed by the PCI / PCI-X bus architectures. Similarly, a spread-spectrum clock input, within the archi-
tectural bounds, is supported for either or both interfaces.
The bridge contains a separate internal phase-locked loop (PLL) circuit for each clocking domain. The PLL for
each interface is employed when its bus is running in PCI-X mode, as determined by the bus initialization
process described below. When either bus is running in PCI mode, the respective PLL is bypassed to allow
for any clock frequency from zero to 66 MHz.
6.2 Clock Jitter
Clock jitter is defined as the relationship of one clock edge to a subsequent clock edge, measured at the
same point. If these two edges are separated by one clock cycle, it is called cycle-to-cycle or short term jitter;
if they are separated by hundreds or thousands of cycles, it is called long term jitter. As specified in
Information on page 125, the IBM 133 PCI-X Bridge R1.1 tolerates a maximum of ± 250 ps of short term and
long term jitter on each of its clock inputs. Clock jitter introduced by the internal PLLs of the bridge is
accounted for within this maximum specification.
As indicated in the PCI and PCI-X architectures, all sources of clock jitter must be considered by the system
designer when determining the bus clock frequency. The minimum and maximum clock period specifications
must not be violated for any single clock cycle. System designers must assure that the system clock output
period, including all sources of clock period variation such as jitter and component tolerances, will always be
within the minimum and maximum limits defined for the mode in which the bus is configured. For example, if
a specific system clock design has a maximum clock period variation of 180 ps, then the nominal clock period
for the PCI-X 133 range needs to be at least 7.68 ns (7.5 ns + 0.180 ns) to account for it. This means that the
maximum frequency allowed for this case is just over 130 MHz. Thus, one can see that careful design of the
clock generation circuitry is an important factor in determining the speed of the bus.
6.3 Mode and Clock Frequency Determination
As explained in Sections 6.2 and 8.9 of the
PCI-X Addendum to the PCI Local Bus Specification, the mode
and frequency range of each bus is determined by the values on its M66EN and PCIXCAP signals when the
bus reset signal is active. Each bus client is then informed of the determination via an initialization pattern that
is broadcast at the de-assertion or rising edge of the reset signal. This process is accomplished on the
secondary interface differently than on the primary interface, due to architectural requirements for PCI-X
bridges. The details for each are given below.
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