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| 型號(hào)： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 123/140頁(yè) |
| 文件大小： | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_pcix_regs.fm.03
July 9, 2001
Configuration Registers
Page 75 of 131
5.2.5.19 PCI-X Secondary Status Register
The PCI-X Secondary Status register reports status information about the secondary interface.
Address Offset
x‘82’
Access
See individual bit descriptions. Reads to this register behave normally. Writes are
slightly different in that bits can be reset, but not set. A bit is reset whenever the
register is written, and the data in the corresponding bit location is a ‘1’.
Reset Value
x‘0003’
Re
s
e
rv
ed
S
e
condar
y
Cloc
k
F
requ
ency
S
p
lit
R
equest
D
elaye
d
S
p
lit
C
omplet
io
n
O
verr
un
Un
ex
pec
ted
S
plit
Completi
on
S
p
lit
C
omplet
io
n
Disc
a
rded
133
M
H
z
C
apable
64-
bi
t
D
evice
15 14 13 12 11 10
9
876543210
Bit(s)
Access
Field Name and Description
15:9
RO
Reserved.
8:6
RO
Secondary Clock Frequency
This register enables configuration software to determine to what mode and (in PCI-X mode) what frequency
the bridge set the secondary bus the last time secondary RST# was asserted. This is the same information
the bridge used to create the PCI-X initialization pattern on the secondary bus the last time secondary RST#
was asserted.
Value
Max Clock Frequency (MHz) Minimum Clock Period (ns)
000
conventional mode
N/A
001
66
15
010
100
10
011
133
7.5
100
reserved reserved
101
reserved reserved
110
reserved reserved
111
reserved reserved
5RW
Split Request Delayed
This bit is set any time the bridge has a request to forward a transaction to the secondary bus, but cannot
because there is not enough room within the limit specified in the Split Transaction Commitment Limit field in
the Downstream Split Transaction Control register. It is used by algorithms that optimize the setting of the
downstream Split Transaction Commitment Limit register.
0
bridge has not delayed a Split Request.
1
bridge has delayed a Split Request.
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