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參數(shù)資料
| 型號(hào)： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 49/140頁 |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
General Information
Page 8 of 131
ppb11_intro.fm.03
July 9, 2001
2.3 Technology Highlights
The IBM 133 PCI-X Bridge R1.1 is implemented using IBM’s CMOS 6SF technology, which is a 0.25 micron
(
mm) lithography process with a 0.18 mmLeffective. The device requires two power supplies, one at 2.5 V for
internal logic and the other at 3.3 V to power the device I/O circuits. The device is packaged in a 31mm ther-
mally and electrically enhanced Plastic Ball Grid Array (H-PBGA) with 304 balls. See
page 125 and
Mechanical Information on page 127 for further details.
2.4 Block Diagram
As shown in
Figure 1 on page 9, the IBM 133 PCI-X Bridge R1.1 is composed of the following major func-
tional blocks:
Two instances of a PCI-X interface macro, one of the many elements in the IBM Blue Logic Core
Library. Each macro handles the PCI/PCI-X protocol for its respective bus and, depending on the type of
transaction, can act as either a bus master or a bus slave. These macros transfer data and control infor-
mation flowing to and from the blocks shown in the middle of the diagram.
Two phase-locked loops (PLLs), one for the primary clock domain and one for the secondary clock
domain. The PLL for each clock domain is used when that bus is running in PCI-X mode; in PCI mode,
the PLL is bypassed to allow the full frequency range as defined by the bus architecture. The two bus
clocks may be run synchronously or asynchronously. A spread-spectrum clock input, within the architec-
tural bounds, is supported for either or both interfaces.
One set of configuration registers, programmable only from the primary interface. The first 64 bytes of this
address space conform to the architectural format for bridge devices, called Header Type 1. The remain-
ing 192 bytes are device-specific registers. Each register is fully defined in
One data/control unit for downstream transactions and one for upstream transactions. These symmetric
units each contain separate buffers for burst read, posted write, and single data phase operations. Read
and write queues, queue compare logic, address decoding, control logic, and other control functions are
also included in these blocks.
An arbiter for the secondary bus, which can be disabled if an external arbiter is employed. When enabled,
bus arbitration is provided for the IBM 133 PCI-X Bridge R1.1 and up to six other masters. Each client can
be assigned high or low priority, or can be masked off.
A clocking and reset control unit to manage these common device functions.
A JTAG controller, compliant with IEEE Standard 1149.1, to facilitate boundary scan testing.
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