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| 型號： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 35/140頁 |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_preface.fm.03
July 9, 2001
Preface
Page 5 of 131
Downstream
Transactions forwarded from the primary interface to the secondary interface are
said to be flowing downstream, regardless of direction of data flow.
Originating Bus
For transactions that cross the bridge, the bus on which the initiator of a transaction
resides.
Parity
Throughout this specification,
odd parity should be interpreted as meaning that the
total number of bits with a b‘1’ value within a field and its associated parity bit is an
odd number. Similarly,
even parity should be interpreted as meaning that the total
number of bits with a b‘1’ value within a field and its associated parity bit is an even
number.
Primary Interface
The interface connected to the bus closest to the Host Processor.
Reserved Bits
The term reserved is applied to any undefined, unimplemented, or spare bits within
the registers of the device. No assumptions may be made about these bits in any
way, as these bits may have meaning assigned to them in the future. Hence, care
must be taken when accessing registers with reserved bit fields. For read accesses,
such bits should not be expected to have any specific or consistent value, and there-
fore appropriate masks should be used to extract only those bits that are defined.
For write accesses, the values of reserved bit fields should be preserved by
performing a read-modify-write sequence.
Secondary Interface
The interface connected to the bus farthest from the Host Processor.
Upstream
Transactions forwarded from the secondary interface to the primary interface are
said to be flowing upstream, regardless of direction of data flow.
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