參數(shù)資料
型號: IBM21P100BGB
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA304
封裝: 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304
文件頁數(shù): 71/140頁
文件大?。?/td> 2032K
代理商: IBM21P100BGB
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Configuration Registers
Page 28 of 131
ppb11_pcix_regs.fm.03
July 9, 2001
-Revision ID
-Class Code
- Cache Line Size
- Latency Timer
- Header Type
- Built-in Self Test (BIST)
The remaining 48 bytes are the PCI Device Header Type region with registers for:
- Base Address Registers
-Primary Bus Number
- Secondary Bus Number
- Subordinate Bus Number
- Secondary Latency Timer
- I/O Base and Limit
- Secondary Status
- Memory Base and Limit
- Prefetchable Memory Base and Limit
- Prefetchable Base and Limit Upper 32 Bits
- I/O Base and Limit Upper 16 Bits
- Capabilities Pointer
- Expansion ROM Addresses
- Interrupt Line
- Interrupt Pin
- Bridge Control
5.2.2 Summary of Registers
Table 8: Register Summary on page 29 provides a list of these registers and an index to their detailed
descriptions.
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