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| 型號(hào)： | IBM21P100BGB |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 8/140頁(yè) |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_signals.fm.03
July 9, 2001
Signal Descriptions
Page 97 of 131
7.2 Secondary Interface Signals
Table 13: Secondary Interface Signal List (Page 1 of 2)
Signal Name
I/O
Width
Description
S_ACK64#
I/O
1
Acknowledge 64-Bit Transfer
Asserted by the currently addressed target on the secondary bus to indicate its willing-
ness to transfer data using 64 bits.
S_AD(63:00)
I/O
64
Multiplexed Address and Data
These signals are the 64-bit multiplexed address and data bus, shared by other devices
on the secondary bus. During the various phases of a transaction, this bus contains the
physical bus address, attributes, or data, or it may be reserved.
S_C/BE(7:0)#
I/O
8
Multiplexed Bus Command and Byte Enables
During the various phases of a transaction, these eight bits define the bus command,
attributes, or byte enables for the transfer. These signals are shared with other agents
on the secondary bus and at times may be reserved.
S_CLK
I
1
Clock
Received by the bridge and provides timing for all operations on the secondary interface.
S_DEVSEL#
I/O
1
Device Select
Asserted by the target on the secondary bus that decoded the address of the current
transaction as being within one of its address ranges.
S_DEVSEL# is monitored by the bridge when performing a secondary bus transaction
on behalf of a primary bus master.
S_DEVSEL# is driven by the bridge when a secondary bus master is performing a trans-
action on the secondary bus intended for a primary bus slave.
S_FRAME#
I/O
1
Cycle Frame
Defines the beginning and duration of each secondary bus transaction and is controlled
by the initiator of the operation.
S_FRAME# is driven by the bridge when performing a secondary bus transaction on
behalf of a primary bus master.
S_FRAME# is monitored by the bridge when a secondary bus master is performing a
transaction on the secondary bus.
S_GNT1REQ#
O
1
Grant 1
This is a dual-purpose signal:
When the bridge’s internal arbiter is enabled, this signal is used as a grant output, acti-
vated by a the bridge to grant use of the secondary bus to the master who requested use
with the S_REQ1GNT# signal.
When the internal arbiter is disabled, this signal is used by the bridge as its request out-
put signal.
S_GNT2# - S_GNT6#
O
5
Grants 2-6
Driven by the bridge's internal arbiter to grant usage of the secondary bus to the master
that activated the corresponding request signal.
S_IRDY#
I/O
1
Initiator Ready
This signal indicates the ability of the initiator on the secondary bus to complete the cur-
rent data phase of the transaction. It is used in conjunction with S_TRDY#.
S_IRDY# is driven by the bridge when performing a secondary bus transaction on behalf
of a primary bus master.
S_IRDY# is monitored by the bridge when a secondary bus master is performing a trans-
action on the secondary bus through the bridge.
S_LOCK#
I/O
1
Lock
Indicates that an atomic (unbroken) operation is required that may need multiple second-
ary bus transactions to complete.
The bridge drives S_LOCK# only to propagate an exclusive access from the primary bus
to the secondary bus and monitors S_LOCK# as part of that protocol.
When acting as a target on the secondary interface, the bridge ignores S_LOCK#.
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