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| 型號(hào)： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 81/140頁(yè) |
| 文件大?。?/td> | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_pcix_regs.fm.03
July 9, 2001
Configuration Registers
Page 37 of 131
5.2.4.4 Status Register
This register records the status of PCI events.
Address Offset
x‘06’
Access
See individual bit fields. Reads to this register behave normally. Writes are
slightly different in that bits can be reset, but not set. A bit is reset whenever the
register is written, and the data in the corresponding bit location is a ‘1’.
Reset Value
x‘02B0’ in PCI mode, x‘0230’ in PCI-X mode
De
te
ct
ed
Parit
y
E
rror
S
ignaled
S
yst
em
Err
o
r
Re
ceived
Mast
er
Abort
Re
ceived
T
a
rget
Abort
S
ignaled
T
a
rget
A
bort
D
e
vi
ce
Sel
e
ct
T
imi
ng
M
a
st
er
Dat
a
Parit
y
Error
F
a
st
B
a
ck
-t
o-
Back
Capab
le
Re
s
e
rv
ed
66
MH
z
C
apable
Ca
pabi
lit
ie
s
L
ist
Re
s
e
rv
ed
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
15
RW
Detected Parity Error Status
0
Device did not detect a parity error
1
Device detected a parity error
14
RW
Signaled System Error Status
0
Device did not generate a SERR# signal
1
Device generated a SERR# signal
13
RW
Received Master Abort Status
0
Bus master transaction was not terminated with a bus Master Abort
1
Bus master transaction terminated with bus Master Abort
12
RW
Received Target Abort Status
0
Bus master transaction was not terminated by a Target Abort
1
Bus master transaction terminated by a Target Abort
11
RW
Signaled Target Abort Status
0
Target device did not terminate a transaction with a Target Abort
1
Target device terminated a transaction with a Target Abort
10:9
RO
Device Select (DEVSEL) Timing Status
01
Medium
8RW
Data Parity Status
0
No data parity errors encountered
1
Data parity errors encountered (this bit for Bus Masters only)
7RO
Fast Back-to-Back Status
0
Target not capable of accepting fast back-to-back transactions in PCI-X mode
1
Target capable of accepting fast back-to-back transactions in conventional PCI mode
This bit is set by hardware when the primary interface is in PCI mode and is set to a b‘0’ when the primary inter-
face is in PCI-X mode.
6
RO
Reserved
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