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| 型號(hào)： | IBM21P100BGB |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 52/140頁(yè) |
| 文件大小： | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_intro.fm.03
July 9, 2001
General Information
Page 11 of 131
2.5.2.2 Posted Write Buffers
The posted write buffers each have a capacity of 1 KB to hold data from posted memory write transactions.
Each is logically divided into eight independent 128-byte segments to allow transactions to be issued on the
target bus before they have been completed on the initiating bus. Unlike the burst read buffers, the amount of
space assigned to each transaction is dynamic; that is, a single transaction can utilize from one to all eight
128-byte subsections as needed. Hence, each posted write queue is an 8-entry FIFO, and up to eight active
write transactions in each direction are possible. Again, activity generally occurs in the bridge when a 128-
byte segment is filled or emptied, and the design keeps data flowing through the bridge by using or re-using
128-byte subsections as they become available.
2.5.2.3 Single Data Phase Buffers
There is one single data phase buffer for each direction to hold read or write data from 4-byte split or delayed
transactions. These transactions include all I/O or configuration operations as well as doubleword memory
read operations.
2.5.3 Address Decoding
The IBM 133 PCI-X Bridge R1.1 is a transparent bridge and utilizes a flat addressing model, meaning that
both PCI and PCI-X address spaces are split between the primary bus and the secondary bus. Address
ranges residing on the secondary bus are defined by the I/O, Memory, and Prefetchable Memory Base and
Limit registers in the bridge configuration space. All other addresses are assumed to reside on the primary
bus; in other words, inverse address decoding is used to determine when to forward transactions upstream.
The only exception to this is when the optional opaque address range is defined by its Base and Limit regis-
ters and is enabled. By definition, the IBM 133 PCI-X Bridge R1.1 does not recognize transactions on either
bus to addresses within the opaque range. This region may be used, for example, for peer-to-peer communi-
cation between devices on the secondary bus.
The IBM 133 PCI-X Bridge R1.1 supports full 64-bit addressing and handles dual address cycles on both
interfaces. The device provides no capability for translating addresses.
The IBM 133 PCI-X Bridge R1.1 configuration registers are accessible only from the primary interface. There
are no other I/O- or memory-mapped facilities in the device, so the optional Base Address registers 0 and 1 of
the configuration header are not implemented. On the secondary interface, the bridge ignores all configura-
tion read transactions as well as Type 0 configuration write transactions, and it only claims Type 1 configura-
tion write transactions that specify conversion to a special cycle on an upstream bus segment.
2.5.4 Bus Arbitration
The IBM 133 PCI-X Bridge R1.1 contains an arbiter for the secondary interface that is enabled or disabled via
an input signal pin. It provides bus arbitration for up to six additional masters, each of which may be assigned
high or low priority or may be masked off. When the internal arbiter is being used and the IBM 133 PCI-X
Bridge R1.1 request is not masked off, the bus will be parked at the bridge whenever there are no pending
requests.
The arbiter implements a two-level fairness algorithm that allows each device within a level to receive grant
requests cyclically. The arbiter uses the Arbitration Priority register to determine which agents are high
priority (HP) devices and which are low priority (LP) devices. At different points in time, snapshots are taken
of all pending requests at each priority level. All captured HP requests are serviced first, then one of the
captured LP requests is serviced. At this point, a new HP snapshot is taken, picking up any new HP requests,
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