參數(shù)資料
型號： DS3112
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 82/134頁
文件大小： 900K
代理商： DS3112
DS3112
51 of 134
Register Name:
T3E3EIC
Register Description:
T3/E3 Error Insert Control Register
Register Address:
18h
Bit #
7
6
5
4
3
2
1
0
Name
MEIMS
FBEIC1
FBEIC0
FBEI
T3CPBEI
T3PBEI
EXZI
BPVI
Default
000
0
Bit #
151413
121110
9
8
Name
n/a
Default
---
-----
Note: Bits that are underlined are read only; all other bits are read-write.
Bit 0 / BiPolar Violation Insert (BPVI). A 0 to 1 transition on this bit will cause a single BPV to be
inserted into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for
the next occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again
for a subsequent error to be inserted. Toggling this bit has no affect when the T3/E3 interface is in the
Unipolar Mode (see Section 4.2 for details about the Unipolar Mode). In the Manual Error Insert mode
(MEIMS = 1), errors will be inserted on each toggle of the FTMEI input signal as long as this bit is set
high. When this bit is set low, no errors will be inserted.
Bit 1 / EXcessive Zero Insert (EXZI). A 0 to 1 transition on this bit will cause a single EXZ event to be
inserted into the transmit data stream. An EXZ event is defined as three or more consecutive zeros in the
T3 Mode and four or more consecutive zeros in the E3 Mode. Once this bit has been toggled from a 0 to
a 1, the device waits for the next possible B3ZS/HDB3 code word insertion and it suppresses that code
word from being inserted and hence this creates the EXZ event. This bit must be cleared and set again for
a subsequent error to be inserted. Toggling this bit has no affect when the T3/E3 interface is in the
Unipolar Mode (see Section 4.2 for details about the Unipolar Mode). In the Manual Error Insert mode
(MEIMS = 1), errors will be inserted on each toggle of the FTMEI input signal as long as this bit is set
high. When this bit is set low, no errors will be inserted.
Bit 2 / T3 Parity Bit Error Insert (T3PBEI). A 0 to 1 transition on this bit will cause a single T3 Parity
error event to be inserted into the transmit data stream. A T3 Parity event is defined as flipping the
proper polarity of both the P Bits in a T3 Frame (see Section 15.2 for details about the P Bits). Once this
bit has been toggled from a 0 to a 1, the device waits for the next T3 frame to flip both P Bits. This bit
must be cleared and set again for a subsequent error to be inserted. Toggling this bit has no affect when
the device is operated in the E3 Mode. In the Manual Error Insert mode (MEIMS = 1), errors will be
inserted on each toggle of the FTMEI input signal as long as this bit is set high. When this bit is set low,
no errors will be inserted.
相關PDF資料
PDF描述
DS3131 SPECIALTY TELECOM CIRCUIT, PBGA256
DS3134 DATACOM, FRAMER, PBGA256
DS3150QN DATACOM, PCM TRANSCEIVER, PQCC28
DS3150Q DATACOM, PCM TRANSCEIVER, PQCC28
DS3150TN DATACOM, PCM TRANSCEIVER, PDIP48
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