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參數(shù)資料
| 型號(hào)： | DS3112 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁(yè)數(shù)： | 60/134頁(yè) |
| 文件大小： | 900K |
| 代理商： | DS3112 |
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DS3112
31 of 134
SECTION 4: MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT
4.1 MASTER RESET AND ID REGISTER DESCRIPTION
The Master Reset and ID (MRID) register can be used to globally reset the device. When the RST bit is
set to one, all of the internal registers will be placed into their default state which is 0000h. A reset can
also be invoked by the RST* hardware signal.
The upper byte of the MRID register is read only and it can be read by the Host to determine the chip
revision. Contact the factory for specifics on the meaning of the value read from the ID0 to ID7 bits.
Register Name:
MRID
Register Description:
Master Reset and ID Register
Register Address:
00h
Bit #
7
6
5
4
3
2
1
0
Name
n/a
T3E3RSY T2E2RSY
RFIFOR
RST
Default
-
0
Bit #
15
141312
1110
9
8
Name
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Default
1
010
000
1
Note: Bits that are underlined are read only; all other bits are read-write.
Bit 0 / Master Software Reset (RST). When this bit is set to a one by the Host, it will force all of the
internal registers to their default state which is 0000h and forces the T3/E3 and T1/E1 outputs to send an
all ones pattern. This bit must be set high for a minimum of 100ns. This software bit is logically OR’ed
with the hardware signal RST*.
0 = normal operation
1 = force all internal registers to their default value of 0000h
Bit 1 / Low Speed (T1/E1) Receive FIFO Reset (RFIFOR). A 0 to 1 transition on this bit will cause
the receive T1/E1 demux FIFOs to be reset which will causes them to be flushed. See the DS3112 Block
Diagrams in Figures 1A and 1B for details on the placement of the FIFOs within the chip. This bit must
be cleared and set again for a subsequent reset to occur.
Bit 2 / T2/E2/G747 Force Receive Framer Resynchronization (T2E2RSY). A 0 to 1 transition on this
bit will cause all seven of the T2 receive framers or all four of the E2 receive framers or all seven of the
G747 framers to resynchronize. This bit must be cleared and set again for a subsequent resynchronization
to occur.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3131 | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112D1 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112D1+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
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