參數(shù)資料
型號: DS3112
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 121/134頁
文件大?。?/td> 900K
代理商: DS3112
DS3112
87 of 134
Register Name:
BERTBC0
Register Description:
BERT 32-Bit Bit Counter (lower word)
Register Address:
78h
Bit #
765
43210
Name
BBC7
BBC6
BBC5
BBC4
BBC3
BBC2
BBC1
BBC0
Default
000
00000
Bit #
151413
121110
9
8
Name
BBC15
BBC14
BBC13
BBC12
BBC11
BBC10
BBC9
BBC8
Default
000
00000
Register Name:
BERTBC1
Register Description:
BERT 32-Bit Bit Counter (upper word)
Register Address:
7Ah
Bit #
765
43210
Name
BBC23
BBC22
BBC21
BBC20
BBC19
BBC18
BBC17
BBC16
Default
000
00000
Bit #
151413
121110
9
8
Name
BBC31
BBC30
BBC29
BBC28
BBC27
BBC26
BBC25
BBC24
Default
000
00000
Note: Bits that are underlined are read only; all other bits are read-write.
Bits 0 to 31 / BERT 32-Bit Bit Counter (BBC0 to BBC31).
This 32-bit counter will increment for
each data bit (i.e. clock received).
This counter is not disabled when the receive BERT loses
synchronization. This counter can be cleared by toggling the LC control bit in BERTC0. This counter
saturates and will not rollover. Upon saturation, the BBCO status bit in the BERTEC0 register will be
set. This error counter starts counting when the BERT goes into receive synchronization (RLOS = 0 or
SYNC = 1) and it will not stop counting when the BERT loses synchronization. It is recommended that
the Host toggle the LC bit in BERTC0 register once the BERT has synchronized and then toggle the LC
bit again when the error checking period is complete. If the device loses synchronization during this
period, then the counting results are suspect.
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