參數(shù)資料
型號: DS3112
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 111/134頁
文件大?。?/td> 900K
代理商: DS3112
DS3112
78 of 134
7.3 T1 LINE LOOPBACK COMMAND STATUS REGISTER DESCRIPTION
Register Name:
T1LBSR1
Register Description:
T1 Line Loopback Command Status Register 1
Register Address:
5Ch
Bit #
765
43210
Name
LLB8
LLB7
LLB6
LLB5
LLB4
LLB3
LLB2
LLB1
Default
---
-----
Bit #
151413
121110
9
8
Name
LLB16
LLB15
LLB14
LLB13
LLB12
LLB11
LLB10
LLB9
Default
---
-----
Note: See Figure 7.3A for details on the signal flow for the status bits in the T1LBSR1 and T1LBSR2
registers.
Note: Bits that are underlined are read only; all other bits are read-write.
Bits 0 to 15 / T1 Line Loopback Command Status for Ports 1 to 16 (LLB1 to LLB16). These read
only real time status bits will be set to a one when the corresponding T2 framer detects that the C3 bit is
the inverse of the C1 and C2 bits for 5 consecutive frames. These bits will be allowed to clear when the
C3 bit is not the inverse of the C1 and C2 bits for 5 consecutive frames. LLB1 corresponds to T1/E1 Port
1, LLB2 corresponds to T1/E1 Port 2, and so on. The setting of any of the bits in T1LBSR1 or T1LBSR2
can cause a hardware interrupt to occur if the T1LB bit in the Interrupt Mask for MSR (IMSR) is set to a
one. In the E3 and G747 Modes, these bits are meaningless and should be ignored.
Register Name:
T1LBSR2
Register Description:
T1 Line Loopback Command Status Register 2
Register Address:
5Eh
Bit #
765
43210
Name
LLB24
LLB23
LLB22
LLB21
LLB20
LLB19
LLB18
LLB17
Default
---
-----
Bit #
151413
121110
9
8
Name
n/a
LLB28
LLB27
LLB26
LLB25
Default
---
-----
Note: Bits that are underlined are read only; all other bits are read-write.
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