參數(shù)資料
型號(hào)： DS3112
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 132/134頁
文件大小： 900K
代理商： DS3112
DS3112
97 of 134
TFL3
TFL2
TFL1
TFL0
Transmit FIFO Level
0
empty to 15 bytes
0
1
16 to 31 bytes
0
1
0
32 to 47 bytes
0
1
48 to 63 bytes
0
1
0
64 to 79 bytes
0
1
0
1
80 to 95 bytes
0
1
0
96 to 111 bytes
0
1
112 to 127 bytes
1
0
128 to 143 bytes
1
0
1
144 to 159 bytes
1
0
1
0
160 to 175 bytes
1
0
1
176 to 191 bytes
1
0
192 to 207 bytes
1
0
1
208 to 223 bytes
1
0
224 to 239 bytes
1
240 to 256 bytes
Bit 12 / Transmit FIFO Empty (TEMPTY). This read only real time status bit will be set to a one
when the transmit FIFO is empty. It will be cleared when the transmit FIFO contains one or more bytes.
This status bit cannot cause a hardware interrupt.
Bit 13 / Receive FIFO Overrun (ROVR). This latched read only event status bit will be set to a one
each time the receive FIFO overruns. This bit will be cleared when read and will not be set again until
another overrun occurs (i.e. the FIFO has been read from and then allowed to fill up again). The setting
of this bit can cause a hardware interrupt to occur if the ROVR bit in the Interrupt Mask for HSR (IHSR)
register is set to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one.
The interrupt will be allowed to clear when this bit is read.
Bit 14 / Receive FIFO Empty (REMPTY). This real time bit will be set to a one when the Receive
FIFO is empty and will be set to a zero when the Receive FIFO is not empty.
Bit 15 / Receive Abort Sequence Detected (RABT). This latched read only event status bit will be set
to a one each time the receive HDLC controller detects 7 or more ones in a row during packet reception.
If the receive HDLC is not currently receiving a packet, then 7 or more ones in a row will not trigger this
status bit. This bit will be cleared when read and will not be set again until another abort is detected (at
least one valid flag must be detected before another abort can be detected). The setting of this bit can
cause a hardware interrupt to occur if the RABT bit in the Interrupt Mask for HSR (IHSR) register is set
to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt
will be allowed to clear when this bit is read.
相關(guān)PDF資料
PDF描述
DS3131 SPECIALTY TELECOM CIRCUIT, PBGA256
DS3134 DATACOM, FRAMER, PBGA256
DS3150QN DATACOM, PCM TRANSCEIVER, PQCC28
DS3150Q DATACOM, PCM TRANSCEIVER, PQCC28
DS3150TN DATACOM, PCM TRANSCEIVER, PDIP48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3112+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112DK 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
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