參數(shù)資料
型號： DS3112
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 129/134頁
文件大?。?/td> 900K
代理商： DS3112
DS3112
94 of 134
Note: Packets with three or less bytes (including the CRC FCS) in between flags are invalid and the data
that appears in the FIFO in such instances is meaningless. If only one byte is received between flags,
then both the CBYTE and OBYTE bits will be set. If two bytes are received, then OBYTE will be set for
the first one received and CBYTE will be set for the second byte received. If three bytes are received,
then OBYTE will be set for the first one received and CBYTE will be set for the third byte received. In
all of these cases, the Packet Status will be reported as PS0 = 0 / PS1 = 1 and the data in the FIFO should
be ignored.
Bits 0 to 7 / Receive FIFO Data (D0 to D7). Data from the Receive FIFO can be read from these bits.
D0 is the LSB and is received first while D7 is the MSB and is received last.
Bit 8 / Opening Byte (OBYTE). This bit will be set to a one when the byte available at the D0 to D7
bits from the Receive FIFO is the first byte of a HDLC packet.
Bit 9 / Closing Byte (CBYTE). This bit will be set to a one when the byte available at the D0 to D7 bits
from the Receive FIFO is the last byte of a HDLC packet whether the packet is valid or not. The Host
can use the PS0 and PS1 bits to determine if the packet is valid or not.
Bits 10 and 11 / Packet Status Bits 0 and 1 (PS0 and PS1). These bits are only valid when the CBYTE
bit is set to a one. These bits inform the Host of the validity of the incoming packet and the cause of the
problem if the packet was received in error.
PS1
PS0
Packet Status
Reason for Invalid Reception of the Packet
0
Valid
0
1
Invalid
corrupt CRC
1
0
Invalid
incoming packet was either too short (3 or less bytes
including the CRC) or did not contain an integral number
of octets
1
Invalid
abort sequence detected
Register Name:
THDLC
Register Description:
Transmit HDLC FIFO
Register Address:
84h
Bit #
765
43210
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
000
00000
Bit #
151413
121110
9
8
Name
n/a
TMEND
Default
---
----
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3112+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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