參數(shù)資料
型號(hào)： DS3112
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 131/134頁
文件大小： 900K
代理商： DS3112
DS3112
96 of 134
Bit 0 / Transmit Packet End (TEND). This latched read only event status bit will be set to a one each
time the transmit HDLC controller reads a transmit FIFO byte with the corresponding TMEND bit set or
if a FIFO underrun occurs. This bit will be cleared when read and will not be set again until another
message end is detected. The setting of this bit can cause a hardware interrupt to occur if the TEND bit in
the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
Bit 2 / Transmit FIFO Low Water Mark (TLWM). This read only real time status bit will be set to a
one when the transmit FIFO contains less than the number of bytes configured by the Transmit Low
Water Mark Setting control bits (TLWMS0 to TLWMS2) in the HDLC Control Register (HCR). This bit
will be cleared when the FIFO fills beyond the Low Water Mark. The setting of this bit can cause a
hardware interrupt to occur if the TLWM bit in the Interrupt Mask for HSR (IHSR) register is set to a one
and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one.
Bit 4 / Receive FIFO High Water Mark (RHWM). This read only real time status bit will be set to a
one when the receive FIFO contains more than the number of bytes configured by the Receive High
Water Mark Setting control bits (RHWMS0 to RHWMS2) in the HDLC Control Register (HCR). This
bit will be cleared when the FIFO empties below the High Water Mark. The setting of this bit can cause
a hardware interrupt to occur if the RHWM bit in the Interrupt Mask for HSR (IHSR) register is set to a
one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one.
Bit 5 / Receive Packet Start (RPS). This latched read only event status bit will be set to a one each time
the HDLC controller detects an opening byte of an HDLC packet. This bit will be cleared when read and
will not be set again until another message is detected. The setting of this bit can cause a hardware
interrupt to occur if the RPS bit in the Interrupt Mask for HSR (IHSR) register is set to a one and the
HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to
clear when this bit is read.
Bit 6 / Receive Packet End (RPE). This latched read only event status bit will be set to a one each time
the HDLC controller detects the finish of a message whether the packet is valid (CRC correct) or not (bad
CRC, abort sequence detected, packet too small, not an integral number of octets, or an overrun
occurred). This bit will be cleared when read and will not be set again until another message end is
detected. The setting of this bit can cause a hardware interrupt to occur if the RPE bit in the Interrupt
Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR)
register is set to a one. The interrupt will be allowed to clear when this bit is read.
Bit 7 / Transmit FIFO Underrun (TUDR). This latched read only event status bit will be set to a one
each time the transmit FIFO underruns and an abort is automatically sent. This bit will be cleared when
read and will not be set again until another underrun occurs (i.e. the FIFO has been written to and then
allowed to empty again). The setting of this bit can cause a hardware interrupt to occur if the TUDR bit
in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
Bits 8 to 11 / Transmit FIFO Level Bits 0 to 3 (TFL0 to TFL3). These read only real time status bits
indicate the current depth of the transmit FIFO with a 16 byte resolution. These status bits cannot cause a
hardware interrupt.
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