參數(shù)資料
型號： DS3112
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 10/134頁
文件大小： 900K
代理商： DS3112
DS3112
107 of 134
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the DS3112 can be sampled at the Boundary Scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the
DS3112 to shift data into the Boundary Scan register via JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS3112. When the EXTEST instruction is latched
in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The Boundary Scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the Boundary Scan register.
BYPASS
When the BYPASS instruction is latched into the parallel Instruction register, JTDI connects to JTDO
through the one-bit Bypass Test register. This allows data to pass from JTDI to JTDO not affecting the
device's normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel Instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register's parallel output. The device ID code will always have a one in the LSB position.
The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed
by 16 bits for the device and 4 bits for the version. The device ID code for the DS3112 is 0000B143h.
HIGHZ
All digital outputs will be placed into a high impedance state. The Bypass Register will be connected
between JTDI and JTDO.
CLAMP
All digital outputs will output data from the boundary scan parallel output while connecting the Bypass
Register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
11.4 TEST REGISTERS
IEEE 1149.1 requires a minimum of two Test registers; the Bypass register and the Boundary Scan
register. An optional Test register has been included in the DS3112 design. This Test register is the
Identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions which provides a short path between JTDI and JTDO.
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DS3131 SPECIALTY TELECOM CIRCUIT, PBGA256
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參數(shù)描述
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