參數(shù)資料
型號(hào)： DS3112
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 123/134頁
文件大?。?/td> 900K
代理商： DS3112
DS3112
89 of 134
Bit 6 / Receive All Ones (RA1). A latched read only alarm status bit which is set when 31 consecutive
ones are received. Allowed to be cleared once a zero is received.
Bits 8 to 15 / BERT 24-Bit Error Counter (BEC0 to BEC7). Lower byte of the 24-bit counter. See the
BERTEC1 register description for details.
BERT Status Bit Flow Figure 8.2A
Note: All event and alarm latches above are cleared when the BERTEC0 register is read.
Register Name:
BERTEC1
Register Description:
BERT 24-Bit Error Counter (upper)
Register Address:
7Eh
Bit #
765
43210
Name
BEC15
BEC14
BEC13
BEC12
BEC11
BEC10
BEC9
BEC8
Default
000
00000
Bit #
151413
121110
9
8
Name
BEC23
BEC22
BEC21
BEC20
BEC19
BEC18
BEC17
BEC16
Default
000
00000
Note: Bits that are underlined are read only; all other bits are read-write.
Bits 0 to 15 / BERT 24-Bit Error Counter (BEC8 to BEC23). Upper two bytes of the 24-bit counter.
This 24-bit counter will increment for each data bit received in error. This counter is not disabled when
the receive BERT loses synchronization. This counter can be cleared by toggling the LC control bit in
BERTBC0. This counter saturates and will not rollover. Upon saturation, the BECO status bit in the
BERTEC0 register will be set. This error counter starts counting when the BERT goes into receive
synchronization (RLOS = 0 or SYNC = 1) and it will not stop counting when the BERT loses
synchronization. It is recommended that the Host toggle the LC bit in BERTC0 register once the BERT
has synchronized and then toggle the LC bit again when the error checking period is complete. If the
device loses synchronization during this period, then the counting results are suspect.
Alarm Latch
Change in State Detect
RLOS
(BERTEC0
Bit 4)
Internal RLOS
Signal from
BERT
Event Latch
Internal Bit
Error Detected
Signal from
BERT
Event Latch
Internal Counter
Overflow
Signal from
BERT
OR
BED
(BERTEC0
Bit 3)
BECO or BBCO
(BERTEC0
Bits 1 & 2)
Mask
BERT
(IMSR Bit 2)
INT*
Hardware
Signal
BERT
Status Bit
(MSR Bit 2)
Mask
IESYNC (BERTC0 Bit 15)
Mask
IEBED (BERTC0 Bit 14)
IEOF (BERTC0 Bit 13)
Event Latch
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