參數(shù)資料
型號(hào): DS3112
廠商: DALLAS SEMICONDUCTOR
元件分類(lèi): Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁(yè)數(shù): 126/134頁(yè)
文件大小: 900K
代理商: DS3112
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)當(dāng)前第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)
DS3112
91 of 134
Transmit Operation
On reset, the transmit HDLC controller will flush the transmit FIFO and transmit an abort followed by
either 7Eh or FFh (depends on the setting of the TFS control bit) continuously. The transmit HDLC then
waits until there are at least two bytes in the transmit FIFO before beginning to send the packet. The
transmit HDLC will automatically add an opening flag of 7Eh to the beginning of the packet and zero
stuff the outgoing datastream. When the transmit HDLC controller detects that the TMEND bit in the
transmit FIFO is set, it will automatically calculate and add in the 16-bit CRC checksum followed by a
closing flag of 7Eh. If the FIFO is empty, then it will begin sending either 7Eh or FFh continuously. If
there is some more data in the FIFO, then the transmit HDLC will automatically add in the opening flag
and begin sending the next packet. Between consecutive packets, there are always at least two flags of
7Eh. If the transmit FIFO ever empties when a packet is being sent (i.e. before the TMEND bit is set),
then the transmit HDLC controller will send an abort of seven ones in a row (FEh) followed by a
continuous transmission of either 7Eh (flags) or FFh (idle) and the Transmit FIFO Underrun (TUDR)
status bit will be set. When the FIFO underruns, the transmit HDLC controller should be reset by the
Host.
The transmit HDLC has been designed to minimize it’s real time Host support requirements. The
transmit FIFO is 256 bytes which is deep enough to store the three T3 packets (Path ID, Idle Signal ID,
and Test Signal ID) that need to be sent once a second. Hence in T3 applications, the Host only needs to
access the transmit HDLC once a second to load up the three messages. Once the Host has loaded an
outgoing packet, it can monitor the Transmit Packet End (TEND) status bit to know when the packet has
finished being transmitted.
Also the Host can be notified when the FIFO has emptied below a
programmable level called the low water mark. The Host must never overfill the FIFO. To keep this
from occurring, the Host can obtain the real time depth of the transmit FIFO via the Transmit FIFO Level
bits in the HDLC Status Register (HSR).
9.2 HDLC CONTROL AND FIFO REGISTER DESCRIPTION
Register Name:
HCR
Register Description:
HDLC Control Register
Register Address:
80h
Bit #
7
654
321
0
Name
n/a
RHR
THR
TFS
n/a
TCRCI
TZSD
TCRCD
Default
-
000
-
0
Bit #
15
14
13
12
11
10
9
8
Name
RHWMS2 RHWMS1
RHWMS0
TLWMS2
TLWMS1
TLWMS0 RID
TID
Default
0
Note: Bits that are underlined are read only; all other bits are read-write.
Bit 0 / Transmit CRC Defeat (TCRCD). When this bit is set low, the HDLC will automatically
calculate and append the 16 bit CRC to the outgoing HDLC message. When this bit is set high, the
device will not append the CRC to the outgoing message.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
相關(guān)PDF資料
PDF描述
DS3131 SPECIALTY TELECOM CIRCUIT, PBGA256
DS3134 DATACOM, FRAMER, PBGA256
DS3150QN DATACOM, PCM TRANSCEIVER, PQCC28
DS3150Q DATACOM, PCM TRANSCEIVER, PQCC28
DS3150TN DATACOM, PCM TRANSCEIVER, PDIP48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3112+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112DK 功能描述:網(wǎng)絡(luò)開(kāi)發(fā)工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類(lèi)型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類(lèi)型:802.11 b/g, Ethernet 工作電源電壓:3.3 V