參數(shù)資料
型號: DS3112
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 3/134頁
文件大?。?/td> 900K
代理商: DS3112
DS3112
100 of 134
SECTION 10: FEAC CONTROLLER
10.1 GENERAL DESCRIPTION
The DS3112 contains an onboard FEAC controller. When the device is operated in the T3 Mode, the
FEAC controller is only active in the C-Bit Parity Mode. When the device is operated in the E3 mode,
the user has the option to connect the FEAC controller to the Sn bit position. On the receive side, the
FEAC controller is always connected to the receive E3 framer. If the Host does not wish to use the
FEAC controller for the Sn bit, then the status updates provided by the FEAC controller are ignored. On
the transmit side, the Host selects the source of the Sn via the E3SnC0 and E3SnC1 controls bits in the
T3/E3 Control Register (see Section 5.2 for details).
The DS3112 can both detect and generate Far End Alarm Codewords (FEAC). The FEAC codeword is a
repeating 16 bit pattern of the form ...0xxxxxx011111111... where the rightmost bit is transmitted first.
The FEAC codeword must be transmitted at least 10 times. When no FEAC codeword is being
transmitted, the data pattern should be forced to all ones.
The receive FEAC detector does a bit by bit search for a data pattern of the form of a FEAC codeword.
Once found, the receive FEAC detector validates incoming codewords by checking to see that the same
codeword is found in three consecutive opportunities. Once validated, a codeword is considered no
longer present when it is received incorrectly twice in a row. Once a codeword is validated, the Receive
FEAC Codeword Detect (RFCD) status bit is set and the codeword is written into the Receive FEAC
FIFO for the Host to read. The Host can use the RFCD status to know when to read the Receive FEAC
FIFO. The Receive FEAC FIFO is four codewords deep. If the FIFO is full when the receive FEAC
detector attempts to write a new incoming codeword, the latest incoming codeword(s) will be discarded
and the Receive FEAC FIFO Overflow (RFFO) status bit will be set.
The DS3112 can transmit two different FEAC codewords. This is useful if the Host wishes to generate a
Loopback Command which is made up of 10 FEAC codewords that indicate the type of loopback
followed by 10 FEAC codewords that indicate which line is to be looped back.
10.2 FEAC CONTROL REGISTER DESCRIPTION
Register Name:
FCR
Register Description:
FEAC Control Register
Register Address:
90h
Bit #
765
43210
Name
TFS1
TFS0
TFCA5
TFCA4
TFCA3
TFCA2
TFCA1
TFCA0
Default
000
00000
Bit #
151413
121110
9
8
Name
RFR
IERFI
TFCB5
TFCB4
TFCB3
TFCB2
TFCB1
TFCB0
Default
0
-
0
00000
Note: Bits that are underlined are read only; all other bits are read-write.
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