參數(shù)資料
型號: AMD-K5
廠商: Advanced Micro Devices, Inc.
英文描述: 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器)
中文描述: 32位卓越的價格/性能值微處理器(32位高性/價比微處理器)
文件頁數(shù): 74/100頁
文件大?。?/td> 2533K
代理商: AMD-K5
64
AMD-K5 Processor Data Sheet
18522F/0—Jan1997
PRELIMINARY INFORMATION
10.3
50-MHz Bus Operation
Table 21. CLK Switching Characteristics for 50-MHz Bus Operation
Symbol
Parameter Description
Advance Info
Min
25 MHz
20.0 ns
Figure
Comments
Max
50 MHz
40.0 ns
±
250 ps
Frequency
CLK Period
t
1
t
1a
t
2
t
3
t
4
t
5
16
CLK Period Stability
Note 1
CLK High Time
4.0 ns
16
@ 2.0 V, Note 1
CLK Low Time
4.0 ns
16
@ 0.8 V, Note 1
CLK Fall Time
0.15 ns
1.5 ns
16
2.0–0.8 V, Note 1
CLK Rise Time
0.15 ns
1.5 ns
16
0.8–2.0 V, Note 1
Notes:
1. Not 100% tested; determined by design characterization.
Table 22. Delay Timing for 50-MHz Bus Operation
Symbol
Parameter Description
Advance Info
Min
Figure
Comments
Max
t
6a
ADSC, BE7–BE0, D/C, PWT, PCD, W/R, CACHE,
SCYC Valid Delay
AP Valid Delay
1.0 ns
7.0 ns
17
t
6b
t
6c
t
6d
1.0 ns
8.5 ns
17
A31–A3, LOCK Valid Delay
1.1 ns
7.0 ns
17
ADS, M/IO Valid Delay
ADS, ADSC, AP, A31–A3, BE7–BE0, CACHE, D/C,
LOCK, M/IO, PCD, PWT, SCYC, W/R Float Delay
APCHK, IERR, FERR Valid Delay
1.0 ns
7.0 ns
17
t
7
10.0 ns
19
t
8a
t
8b
t
9a
t
9b
t
10a
t
10b
t
11
t
12
t
13
1.0 ns
8.3 ns
17
PCHK Valid Delay
1.0 ns
8.3 ns
17
BREQ, HLDA Valid Delay
1.0 ns
8.0 ns
17
SMIACT Valid Delay
1.0 ns
8.0 ns
17
HIT Valid Delay
1.0 ns
8.0 ns
17
HITM Valid Delay
1.1 ns
6.0 ns
17
PRDY Valid Delay
1.0 ns
8.0 ns
17
D63–D0, DP7–DP0 Write Data Valid Delay
1.3 ns
8.5 ns
17
D63–D0, DP7–DP0 Write Data Float Delay
10.0 ns
19
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