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參數(shù)資料
| 型號(hào)： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價(jià)比微處理器) |
| 中文描述： | 32位卓越的價(jià)格/性能值微處理器（32位高性/價(jià)比微處理器） |
| 文件頁數(shù)： | 64/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
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54
AMD-K5 Processor Data Sheet
18522F/0—Jan1997
PRELIMINARY INFORMATION
unpredictable if the I/O instruction restart word is written
when the processor has not generated an SMI on an I/O instruc-
tion boundary. The SMI handler for the second request must
not set the I/O instruction restart word if the system executes
back-to-back SMI requests.
Halt Auto Restart
On entry to the SMI routine, the Halt Auto Restart word
(FF02h) has the value 0001h if the processor was halted when
the SMI occurred. Otherwise, it has a value of 0000h.
If the value is 0001h, the SMI routine may cause a return to the
HALT instruction by returning without modifying the Halt
Auto Restart word. It may cause a return to the instruction
after the halt instruction by clearing the Halt Auto Restart
word.
8.8
Am486
and AMD-K5 Processor Bus Differences
The AMD-K5 processor:
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Data bus is 64 bits, versus the Am486 processor’s 32 bits
Has eight byte-enables and eight data parity pins
Does not support non-cacheable burst cycles
Supports FLUSH as an edge-triggered input
Supports a writeback cache protocol using MESI (The new
CACHE, HIT, HITM, WB/WT, and INV pins are defined to
support this protocol.)
Maintains the state of the internal caches and FPU, while
performing the reset function with the INIT pin
Supports SMM with the input signal SMI and the output sig-
nal SMIACT
Does not allow invalidations every clock or while driving
the address bus
Supports parity checking on addresses and data
Does not support dynamic bus sizing. This eliminates the
need for the Am486 processor signals BS8 and BS16
Includes the SCYC signal to indicate a split cycle during
locked operations. A split cycle crosses a cache line bound-
ary during an atomic operation due to a misaligned refer-
ence
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| AMD-K6-2 | 32 Bit Microprocessor With 64-Kbyte Level-one Cache High-Performance and Multimedia Execution Unit(帶64K字節(jié)緩存和高性能多媒體執(zhí)行單元的32位微處理器) |
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| AMD-K6 | Circular Connector; No. of Contacts:5; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:14-5 RoHS Compliant: No |
| AMD27C64-150PI | 64 Kilobit (8,192 x 8-Bit) CMOS EPROM |
| AMD27C64 | 64 Kilobit (8,192 x 8-Bit) CMOS EPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AMD-K5-PR100ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR120ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR166ABX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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