參數(shù)資料
型號(hào)： AMD-K5
廠商： Advanced Micro Devices, Inc.
英文描述： 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價(jià)比微處理器)
中文描述： 32位卓越的價(jià)格/性能值微處理器（32位高性/價(jià)比微處理器）
文件頁(yè)數(shù)： 7/100頁(yè)
文件大?。?/td> 2533K
代理商： AMD-K5
vii
18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
State Transition Diagram for Stop Clock State Machine. . . . . 29
Bus State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Single Writes (Zero Wait States) . . . . . . . . . . . . . . . . . . . . . . . . 39
Burst Write (One Wait State) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
BOFF Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Locked Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
HOLD/HLDA Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt Acknowledge Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Inquire Cycle (Hit to a Non-Modified Line) . . . . . . . . . . . . . . . 46
Inquire Cycle (Hit to a Modified Line) . . . . . . . . . . . . . . . . . . . 46
Pipelined Cacheable Data Cache Cycle into
a Cacheable Instruction Cache Cycle. . . . . . . . . . . . . . . . . . . . . 49
Pipelined Write Cycle (Could be I/O) into
a Write Cycle (Could be I/O). . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Diagrams Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Output Valid Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Maximum Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . 70
TCK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
TRST Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Test Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
STPCLK Timing (Stop Grant state) . . . . . . . . . . . . . . . . . . . . . . 72
Transition L1 Shared Line to Exclusive. . . . . . . . . . . . . . . . . . . 72
Invalidation to Non-Modified L1 Cache Line . . . . . . . . . . . . . . 73
Invalidation to Modified Line in
L1 Cache (Writeback Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Single Read due to CACHE Inactive (No Wait State) . . . . . . . 74
Single Read due to KEN Not Asserted (One Wait State). . . . . 74
Single Write due to KEN Inactive (No Wait State) . . . . . . . . . 75
Single Write due to CACHE Inactive (One Wait State). . . . . . 75
Burst Read (No Wait State). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Burst Read (One Wait State). . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Burst Write (One Wait State) . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
BOFF Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Locked Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
HOLD/HLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AHOLD Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Special Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
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