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參數(shù)資料
| 型號(hào)： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價(jià)比微處理器) |
| 中文描述： | 32位卓越的價(jià)格/性能值微處理器（32位高性/價(jià)比微處理器） |
| 文件頁數(shù)： | 33/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
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18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
R/S
Run/STOP
The R/S signal provides an edge-sensitive interrupt to stop nor-
mal execution. A falling-edge transition halts execution at the
next instruction boundary. A rising-edge transition, which
must not occur before PRDY is asserted, resumes execution.
Input
SCYC
Split Cycle
SCYC indicates split cycles when LOCK is asserted. This signal
indicates that more than two cycles will be locked together for
misaligned locked transfers.
Output
SMI
System Management Interrupt
SMI allows external logic to request a non-maskable system
management interrupt. Asserting this signal will cause the pro-
cessor to suspend normal execution and enter System Manage-
ment Mode (SMM) at the next instruction boundary.
Input
SMIACT
SMI Active
SMIACT is asserted when the processor is operating in SMM.
Output
STPCLK
Stop Clock
STPCLK, when asserted, causes the processor to complete the
current instruction and issue a stop grant bus cycle. Once the
stop grant is issued, the processor stops the clock, retaining the
ability to execute inquire cycles.
Input
TCK
Test Clock
TCK is a test clock signal. It conforms to the IEEE-1149.1
boundary scan interface.
Input
TDI
Test Data Input
The TDI signal is a serial input for test data and TAP instruc-
tions. The instructions or data are sampled on the rising edge
of the TCK signal.
Input
TDO
Test Data Output
The TDO signal is a serial output for test data and TAP instruc-
tions. TDO is updated on the falling edge of the TCK signal.
Output
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相關(guān)代理商/技術(shù)參數(shù) |
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