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參數(shù)資料
| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
| 中文描述： | 32位卓越的價格/性能值微處理器（32位高性/價比微處理器） |
| 文件頁數(shù)： | 55/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
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45
18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
Interrupt
Acknowledge
An interrupt acknowledge cycle, shown in Figure 10 on page
45, is a special cycle generated to acknowledge receipt of an
interrupt at the INTR input. The processor generates an inter-
rupt acknowledge cycle in a locked pair of transactions. The
first transaction acknowledges the interrupt to the external
system. The second transaction provides the interrupt vector
to the processor. An idle cycle is generated between the trans-
actions. An interrupt acknowledge cycle is completed upon
assertion of BRDY. (See Figure 40.)
Figure 10. Interrupt Acknowledge Cycles
Inquire Cycles
An inquire cycle is employed to allow the system to determine
whether a particular line is cached and modified. After obtain-
ing ownership of the address bus using BOFF, AHOLD, or
HOLD, the system drives the physical address of the line on
A31–A5, and marks the address valid with EADS.
If the processor detects a hit in its instruction or data cache,
the processor asserts the HIT signal two clock cycles after the
assertion of EADS (see Figure 11 on page 46). If the line is
modified (see Figure 12 on page 46), the processor asserts the
HITM signal two clocks after the assertion of EADS, and writes
back the modified line. EADS is ignored during the writeback
of the modified line. Initiation of the writeback of the modified
line will occur no earlier than two clock cycles after HITM is
asserted.
CLK
ADS
BRDY
W/R
LOCK
Data
Address
…
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相關(guān)代理商/技術(shù)參數(shù) |
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