參數(shù)資料
型號(hào)： AMD-K5
廠商： Advanced Micro Devices, Inc.
英文描述： 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價(jià)比微處理器)
中文描述： 32位卓越的價(jià)格/性能值微處理器（32位高性/價(jià)比微處理器）
文件頁數(shù)： 20/100頁
文件大小： 2533K
代理商： AMD-K5
10
AMD-K5 Processor Data Sheet
18522F/0—Jan1997
PRELIMINARY INFORMATION
At the beginning of the decode process, the decoder scans the
x86 instructions and allocates the instructions to the appropri-
ate decode position. This allocation depends on the 5-bit tag
given to each x86 instruction during predecode. When the pre-
decoded instruction passes through the AMD-K5 processor’s
decoder, the number of ROPs needed to equate to the x86
instruction is already known from predecoding, saving valu-
able processing time.
During allocation, the instruction’s pathways are identified. If
an x86 instruction requires less than four ROPs for conversion,
it is sent immediately to any of the four decode positions (Fast-
path). Complex x86 instructions requiring four or more ROPs
(or ROP sequences) are transferred to the Microcode ROM
(MROM) for conversion.
Once through the decode position, the ROPs are dispatched in
parallel to reservation stations that reside in each of the pro-
cessor’s six execution units. A reservation station precedes the
input to individual execution units. Each execution unit has a
pair of reservation stations.
The processor sends ROPs to the reservation stations in order,
but when the ROPs are passed on to the execution units they
can be executed out of order because the reservation stations
can empty at different times. Out-of-order execution elimi-
nates the need for compiler-specific optimization and reduces
dependencies. The ROPs wait in the reservation stations for
the execution unit processing to complete and for the needed
operands, which come from the register file, the data cache, or
are forwarded from other execution units. As an execution unit
finishes processing one instruction, it receives another instruc-
tion from the reservation station. Using reservation stations in
this manner, the processor minimizes instruction stalls due to
dependencies on execution resources and allows a higher issue
rate to be maintained.
4.9
Reorder Buffer
The AMD-K5 processor uses a central reorder buffer—a key to
supporting speculative out-of-order execution (issue and com-
pletion). The central reorder buffer is used to rename regis-
ters, provide subsequent forwarding of requested intermediate
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參數(shù)描述
AMD-K5-PR100ABQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
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AMD-K5-PR133ABQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
AMD-K5-PR133ABR 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
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