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參數(shù)資料
| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
| 中文描述： | 32位卓越的價格/性能值微處理器（32位高性/價比微處理器） |
| 文件頁數(shù)： | 34/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
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24
AMD-K5 Processor Data Sheet
18522F/0—Jan1997
PRELIMINARY INFORMATION
TMS
Test Mode Select
The TMS signal is used to select the TAP Test modes. This sig-
nal is sampled on the rising edge of the TCK. TMS has an inter-
nal pull-up resistor.
Input
TRST
Test Reset
Asserting TRST initializes the TAP controller.
Input
W/R
Write/Read
The W/R signal is used with other control signals to distinguish
bus cycles and special cycles. These cycles are defined in Table
5 and Table 6 on page 27. W/R is driven active with ADS, and
floated with BOFF and bus hold.
Output
WB/WT
Writeback/Writethrough
The state of WB/WT determines the MESI cache protocol state
of a data line during cache line fills. When the signal is driven
High, the cache line will be loaded in the exclusive state. When
the signal is driven Low, the cache line will be loaded in the
shared state.
Input
Table 1.
Input Pins
Name
A20M
AHOLD
BF
BOFF
BRDY
BRDYC
BUSCHK
Type
Note
Note 1
Name
IGNNE
INIT
INTR
INV
KEN
NA
NMI
Type
Note
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Note 2
Note 5
Note 6
Note 3
Notes:
1. A20M may change during RESET or during a serializing event like an I/O write. A state change at other times will result in incorrect
address generation on subsequent memory cycles.
2. BF and FRCMC are normally connected to V
CC
or V
SS
by a jumper. For correct operation, any change on these signals should be
followed by a RESET.
3. BUSCHK is sampled in every clock. Any asserted sample is remembered and takes effect on the same clock as the last BRDY.
4. These are sampled in the same clock as BRDY.
5. This is sampled in the same clock as EADS.
6. These are sampled with the first BRDY or NA and must meet setup to every clock
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