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參數(shù)資料
| 型號(hào)： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價(jià)比微處理器) |
| 中文描述： | 32位卓越的價(jià)格/性能值微處理器（32位高性/價(jià)比微處理器） |
| 文件頁數(shù)： | 25/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
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15
18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
AP
Address Parity
The AP signal provides even parity for the address bus. This
signal is driven simultaneously with the address bus. Inquire
cycles that do not provide even parity in the same clock cycle
as EADS will result in the assertion of APCHK. (See APCHK.)
Input/Output
APCHK
Address Parity Check
If the processor detects an address parity error on the address
bus for inquire cycles, APCHK is asserted on the second clock
after EADS is sampled . It remains active for one clock.
Output
BE7
–BE0
Byte Enables
The BE7
–BE0 signals indicate active bytes during read and
write cycles. The eight byte-enable signals correspond to the
eight bytes of the data bus as follows:
Output
These signals are driven at the same time as the address bus.
The byte-enable signals are also used to decode special cycles
as defined in Table 6.
BF (Model 0)
Bus Frequency
For the AMD-K5 Model 0 processor, the BF signal determines
the internal operating speed of the processor. The frequency of
the CLK signal is multiplied internally by a ratio determined
by the state of the BF signal during RESET. If BF is sampled
High at RESET, the clock frequency is 1.5x the bus frequency.
If BF is sampled Low at RESET, the clock frequency is 2x the
bus frequency.
Input
I
BE7: D63–D56
BE6: D55–D48
BE5: D47–D40
BE4: D39–D32
I
BE3: D31–D24
BE2: D23–D16
BE1: D15–D8
BE0: D7–D0
I
I
I
I
I
I
BF Pin
0
1
Internal Clock Multiplier
2
1.5
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