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| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
| 中文描述： | 32位卓越的價格/性能值微處理器（32位高性/價比微處理器） |
| 文件頁數(shù)： | 43/100頁 |
| 文件大小： | 2533K |
| 代理商： | AMD-K5 |
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33
18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
The INVD instruction invalidates the entire cache and gener-
ates a Flush special cycle to instruct the L2 cache to invalidate
all lines.
The WBINVD instruction writes back and invalidates all cache
lines, generates a Write Back special cycle to instruct the L2
cache to write back all lines, and then generates a Flush spe-
cial cycle to instruct the L2 cache to invalidate all lines.
Read Cycles
The cache response to processor-generated reads is described
in Table 8. Processor reads that hit in the data cache require
no external data cycle. The data is provided by the cache. Pro-
cessor reads that miss in the data cache generate a read-allo-
cate operation, including an external bus cycle. The action of
the cache is dependent on the system response to that cycle.
The cache state transition for read cycles is also described in
Table 8.
A read allocate begins by selecting the way in the cache to be
replaced at random.
If the selected line is
not
modified, the data is discarded and
the read of the new line is begun. When the first quad word of
Table 8.
Processor Reads to Data Cache
State
M
E
S
I
I
I
I
Notes:
CACHE
x
x
x
0
0
1
x
KEN
x
x
x
0
0
x
1
WB/WT
x
x
x
1
0
x
x
PWT
x
x
x
0
x
x
x
Next State
M
E
S
E
S
I
I
Note
1
1
1
2
3
4
4, 5
1. A read cycle hit: Data is provided directly from the cache.
2. A read cycle miss: Selects the line for replacement; writes back the replaced line if it is modified
(otherwise, discards the line). The line is cached as writeback.
3. A read cycle miss: Selects the line for replacement; writes back the replaced line if it is modified
(otherwise discards the line). The line is cached as writethrough.
4. A read cycle miss: The line is not cacheable.
5. Within the cache directory, the Invalid state indicates that the cache entry contains no valid
data. For purposes of hit/miss determination, the Invalid state indicates that the referenced
cache line is not present in the cache. When a line is selected for replacement, all invalid ways
are selected before any valid data is displaced from the cache.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AMD-K5-PR100ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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| AMD-K5-PR133ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR166ABX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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