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參數資料
| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
| 中文描述： | 32位卓越的價格/性能值微處理器（32位高性/價比微處理器） |
| 文件頁數： | 44/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
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34
AMD-K5 Processor Data Sheet
18522F/0—Jan1997
PRELIMINARY INFORMATION
the new line is received, it is forwarded to the execution units.
When all four quad words are available, they are copied to the
cache line at the selected way and the cache status is updated.
If the selected line is modified, the read of the new line is
begun at the same time the contents of the replaced line are
copied to the copy-back buffer. When the first quad word of
the new line is received, it is forwarded to the execution units.
Execution continues concurrently as the rest of the block is
received. When all four quad words are available, they are cop-
ied to the cache line at the selected way and the cache status is
updated. Concurrently, the contents of the replaced line are
written to memory.
Write Cycles
Processor writes that hit in modified or exclusive lines in the
data cache require no external data cycle. The data is updated
in the cache. Processor writes that hit shared lines of the data
cache update the data cache and memory. The status returned
with the writethrough bus cycle determines the final state of
the line.
If write allocate is enabled in the AMD-K5 processor, processor
writes that miss in the data cache generate an external data
cache read cycle followed by a write hit. If write allocate is not
enabled in the AMD-K5 processor, write misses generate an
external write cycle only.
Write Allocate
Write allocate is an operating mode of the AMD-K5 processor
that causes cache write misses to either proceed as normal
write misses or to be converted to data cache line fills followed
by cache write hits. The write allocate feature provides
improved performance on repeat accesses to write-allocated
data cache lines. The load/store unit in the processor deter-
mines whether each cache write miss is write-allocatable by
whether it falls in or out of the ranges specified in the memory
range registers.
For details on the implementation of write allocate, refer to
the
AMD-K5 Processor Software Development Guide
, order#
20007.
Before the write cycle occurs for a write miss with write allo-
cate enabled, an external data cache read cycle occurs that fol-
lows the normal rules for read allocate, and the intermediate
state of the filled data cache line depends on the result of the
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AMD-K5-PR100ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR120ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR166ABX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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