參數(shù)資料
型號(hào)： AMD-K5
廠商： Advanced Micro Devices, Inc.
英文描述： 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價(jià)比微處理器)
中文描述： 32位卓越的價(jià)格/性能值微處理器（32位高性/價(jià)比微處理器）
文件頁(yè)數(shù)： 31/100頁(yè)
文件大小： 2533K
代理商： AMD-K5
21
18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
INV
Invalidation
The INV signal is used to designate the MESI protocol state of
the cache line for inquire cycles that result in hits. This signal
is sampled on the same clock that EADS is asserted. Sampling
INV Low will result in the shared state, while sampling INV
High will result in the invalid state.
Input
KEN
Cache Enable
KEN is asserted to enable caching. Caching is disabled when
KEN is negated. Returning KEN asserted with the first BRDY
or NA of a cacheable cycle causes the line to be placed in the
cache. Returning it negated transforms the cycle into a non-
cacheable, single-cycle read. KEN has a small internal pull-up
resistor. (See Switching Characteristics t
18a
and
t
19
.)
Input
LOCK
Bus Lock
The LOCK signal is asserted to indicate locked cycles, and is
asserted during the first clock of a locked cycle. It is negated
after BRDY is sampled for the last locked bus cycle. A HOLD
request will not be acknowledged during locked cycles, but
AHOLD and BOFF are allowed during locked cycles.
Output
M/IO
Memory/ Input-Output
The M/IO signal is used with other control signals to determine
bus cycle type. These cycles are defined in Table 5 and Table 6
on page 27. M/IO is driven active with ADS.
OUTPUT
NA
Next Address
Input
NA is asserted when external memory is prepared to accept a
pipelined cycle. NA does not generate pipelined cycles when
LOCK is asserted, during writeback cycles, or when there are
no pending internal cycles. Furthermore, locked or writeback
cycles are not pipelined. KEN and WB/WT are sampled when
NA or BRDY is asserted, whichever comes first.
NMI
Non-maskable Interrupt
Asserting the NMI signal generates a non-maskable interrupt.
The NMI input is rising-edge sensitive. The NMI signal must be
held Low for at least one clock before its rising edge.
Input
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