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| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
| 中文描述： | 32位卓越的價格/性能值微處理器（32位高性/價比微處理器） |
| 文件頁數(shù)： | 45/100頁 |
| 文件大小： | 2533K |
| 代理商： | AMD-K5 |
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35
18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
read cycle as shown in Table 8. The final state of the data
cache line is determined as shown in Table 9 by the transition
from the intermediate read state (M, E, S, or I) to the final
state (M, E, S, or I) after the write hit to the cache line.
Note:
In write allocate mode, replaced data cache lines are han-
dled in the same way as during read allocate.
External Inquire
Cycles
The processor supports inquire cycles for both instruction and
data caches to maintain cache coherency. Inquire cycles are
initiated with the assertion of EADS and result in a snoop to
both the instruction and data caches. The snoop operation is
performed using the physical tag arrays that are maintained
for this purpose. The snoop operation runs concurrently with
internal processor operation. The results of the snoop opera-
tion are indicated on the HIT and HITM pins. The results of the
inquire cycles are described in Table 10. (See Figure 25 on
page 72 and Figure 26 on page 73.)
Table 9.
Writes to Data Cache
State
M
E
S
CACHE
x
x
0
0
0
x
KEN
x
x
0
0
0
x
WB/WT
x
x
1
0
x
x
PWT
x
x
0
x
1
x
Next State
M
M
E
Note
1
2
3
S
S
3
I
I
4
Notes:
1. A write hit to modified line: writes data to the cache.
2. A write hit to exclusive line: writes data to the cache.
3. A write hit to shared line: writes data to the cache and memory; invalidates any shared copy
in the other cache.
4. If write allocate mode is not enabled, an invalid line always remains invalid. If write allocate
mode is enabled, the intermediate state of the filled data cache line depends on the result
of the read cycle as shown in Table 8, and the final state of the data cache line is determined
by the intermediate state as applied to this table.
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相關代理商/技術參數(shù) |
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