參數(shù)資料
型號(hào)： AMD-K5
廠商： Advanced Micro Devices, Inc.
英文描述： 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價(jià)比微處理器)
中文描述： 32位卓越的價(jià)格/性能值微處理器（32位高性/價(jià)比微處理器）
文件頁(yè)數(shù)： 27/100頁(yè)
文件大?。?/td> 2533K
代理商： AMD-K5
17
18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
the drive strength is strong. The A31–A22 signals use the weak
drive strength at all times.
BREQ
Bus Request Pending
The processor asserts the BREQ signal to indicate a request for
the bus. This signal is driven even when the processor floats
the bus (except in Test mode). (See FLUSH.)
Output
BUSCHK
Bus Check
The BUSCHK signal allows the external system to indicate bus
cycle errors.
This signal, when asserted, latchs the address bus.
The control signals in the machine check registers will also
latch. If the MCE bit in CR4 is set, the processor will vector to
the machine check exception at the end of the bus cycle. At the
falling edge of RESET, the states of BRDYC and BUSCHK con-
trol the drive strength on the A21–A3 (not including A31–A22),
ADS, HITM, and W/R signals. The drive strength is weak for all
states of BRDYC and BUSCHK except BRDYC and BUSCHK
both Low, in which case drive strength is strong. A31–A22 use
the weak drive strength at all times.
Input
CACHE
Cache Status
The CACHE signal is asserted for cacheable read cycles or
burst writeback cycles. A burst access is always four 64-bit
transfers associated with a line refill or a cache write back.
Read data will not be cached if CACHE is negated during a
read cycle, or if KEN is negated. KEN must be asserted during
the first access of a burst transfer. If KEN is negated, a single
access occurs.
Output
CLK
Clock
The CLK signal is the bus clock for the processor, and is the
primary reference for all bus cycle timings (except for test sig-
nals). It is used with the BF signal to determine the internal
operating speed of the processor. The processor multiplies the
clock input by 1.5 or 2. (See BF.)
Input
D/C
Data/Code
The D/C signal, driven active with ADS, is used with other con-
trol signals to determine bus cycle and special cycle types. It is
floated with BOFF and bus hold. These cycles are defined in
Table 5 and Table 6 on page 27.
Output
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