- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366557 > AMD-K5 (Advanced Micro Devices, Inc.) 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) PDF資料下載
參數(shù)資料
| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
| 中文描述： | 32位卓越的價格/性能值微處理器（32位高性/價比微處理器） |
| 文件頁數(shù)： | 41/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當(dāng)前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁
31
18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
interrupt, or maskable interrupt), recognition of STPCLK is
delayed until the interrupt processing is complete. However,
assertion of a higher priority interrupt will not cause the Stop
Grant State to be exited.
Stop Clock Snoop
State
In this state, all internal clocks are running and an inquire
cycle is being performed. Instruction execution is disabled and
HOLD/HLDA operate normally.
Stop Clock Snoop State is entered from Halt/Auto-Power-Down
State or Stop Grant State when an inquire cycle is detected.
This is a temporary state, lasting only until the coherency oper-
ation (snoop/miss, snoop/invalidate or snoop/writeback) is com-
plete. The clock state will then return to the previous state.
(See Figure 24 on page 72.)
Stop Clock State
In this state, all internal clocks are stopped, the PLL is shut
down, and all execution is disabled. If HOLD is asserted while
the clock is running, HLDA will be generated and the buses
floated. If HOLD is negated, HLDA will be negated and the
buses will be driven to their previous state without regard to
whether the clock is running. This is the lowest power state.
The Stop Clock State is entered from the Stop Grant State by
stopping the CLK. The clock state returns to Stop Grant State
when the CLK is again started. The time required to restart the
CLK and enter the Stop Clock State is approximately 1000
clock cycles.
8.3
Cache Protocol
Internal Cache
The AMD-K5 processor has a 16-Kbyte dual-tagged instruction
cache with 32-byte lines and an 8-Kbyte dual-tagged data cache
of 32-byte lines. Cache lines refill in four transfer burst cycles
from memory and align along 32-byte lines.
The operating mode is software-controlled, and on-chip caches
must be enabled by software. This is accomplished by clearing
or setting the CD and NW bits of CR0.
Any area of memory can be cached. Software can prevent
areas of memory from being cached by setting the PCD bit in
the corresponding page table entry. Hardware can prevent
areas of memory from being cached through the KEN pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AMD-K6-2 | 32 Bit Microprocessor With 64-Kbyte Level-one Cache High-Performance and Multimedia Execution Unit(帶64K字節(jié)緩存和高性能多媒體執(zhí)行單元的32位微處理器) |
| AMD-K6-III | 32-Bit Microprocessor Advanced RISC86 Superscalar Microarchitecture and 3D Technology(32位微處理器帶3D技術(shù)和高級的RISC86超標(biāo)量微體系結(jié)構(gòu)) |
| AMD-K6 | Circular Connector; No. of Contacts:5; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:14-5 RoHS Compliant: No |
| AMD27C64-150PI | 64 Kilobit (8,192 x 8-Bit) CMOS EPROM |
| AMD27C64 | 64 Kilobit (8,192 x 8-Bit) CMOS EPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AMD-K5-PR100ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR120ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR166ABX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。