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參數(shù)資料
| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
| 中文描述： | 32位卓越的價格/性能值微處理器（32位高性/價比微處理器） |
| 文件頁數(shù)： | 46/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
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36
AMD-K5 Processor Data Sheet
18522F/0—Jan1997
PRELIMINARY INFORMATION
Instruction Cache
Coherency
The instruction cache protocol is a subset of the data cache
protocol where only Invalid and Shared states are imple-
mented. Read hits provide the data to the processor. Read
misses result in a read allocate operation that loads the line
into the cache and the data is provided to the processor. The
first data is provided as soon as it arrives from memory.
Write cycles are never generated to the instruction cache, but
inquire cycles may hit in the instruction cache, resulting in the
cache line being invalidated.
Self-Modifying Code
and the Cache
A snoop write hit to the instruction cache is treated as self-
modifying code. The cache line is invalidated and all instruc-
tions in the instruction pipeline are flushed. Execution restarts
at the instruction following the one causing the snoop. This
guarantees exact execution of cacheable self-modifying code.
For non-cacheable code, a jump should be placed between the
modification of the code and its execution.
8.5
External Bus Description
The AMD-K5 processor external bus is identical to the P54C
64-bit bus, and will run at 1.5x or 2.0x multiples of the external
bus frequency. The bus state transitions are illustrated in
Figure 4.
Table 10. Inquire Cycles to Data Cache
State
INV
0
Next State
S
Note
M
Snoop hit to modified line:
Assert HIT and HITM, Write back modified data to
memory, Negate HITM, Transition cache state when
complete.
1
I
E
0
1
0
1
x
S
I
S
I
I
Snoop hit to unmodified line:
Assert HIT, Transition cache state
S
Snoop hit to unmodified line:
Assert HIT, Transition cache state
I
Snoop miss: Negate HIT.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AMD-K5-PR100ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR120ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR166ABX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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