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參數(shù)資料
| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價(jià)比微處理器) |
| 中文描述： | 32位卓越的價(jià)格/性能值微處理器（32位高性/價(jià)比微處理器） |
| 文件頁數(shù)： | 19/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
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9
18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
a given memory location returns valid data. Each cache line is
assigned one of the four protocol states to identify the status of
the information stored in the cache. The writeback cache
design updates memory only when necessary. This keeps the
system bus free for use by other devices and improves the
overall system performance.
4.7
Branch Prediction
A branch
occurs on average once every seven x86 instructions.
When a branch is encountered, the processor predicts which
direction the instruction flow will follow. The AMD-K5 proces-
sor adds branch prediction information to each instruction
cache line in the form of a predicted address tag that indicates
the target address of the first branch that is predicted to be
taken in the cache line.
The processor’s dynamic branch pre-
diction mechanism allows for 1024 branch targets and a 75%
branch prediction accuracy. Combined with a minimal 3-cycle
mispredict penalty, the branch prediction mechanism opti-
mizes the processor’s speculative execution of x86 software,
such as the Microsoft Windows operating system and associ-
ated applications.
The dynamic branch prediction of the processor enables
instructions to be fetched and fed into the processor’s execu-
tion core, eliminating many pipeline bubbles and contributing
to the superior performance of the AMD-K5 processor.
4.8
Unique x86 Instruction Conversion and Decoding
The logical instruction flow within the AMD-K5 processor con-
tinues as up to 32-bytes of predecoded x86 instructions are
fetched from the byte queue of the instruction cache and for-
warded in order to the decoder.
The processor's decoder converts complex x86 instructions into
relatively simple, fast-executing
ROPs that are of fixed length
and easy to process. Simultaneously, the operands needed to
perform the ROPs’ operations are fetched from the register
file or from the reorder buffer.
相關(guān)PDF資料 |
PDF描述 |
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| AMD-K6-2 | 32 Bit Microprocessor With 64-Kbyte Level-one Cache High-Performance and Multimedia Execution Unit(帶64K字節(jié)緩存和高性能多媒體執(zhí)行單元的32位微處理器) |
| AMD-K6-III | 32-Bit Microprocessor Advanced RISC86 Superscalar Microarchitecture and 3D Technology(32位微處理器帶3D技術(shù)和高級的RISC86超標(biāo)量微體系結(jié)構(gòu)) |
| AMD-K6 | Circular Connector; No. of Contacts:5; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:14-5 RoHS Compliant: No |
| AMD27C64-150PI | 64 Kilobit (8,192 x 8-Bit) CMOS EPROM |
| AMD27C64 | 64 Kilobit (8,192 x 8-Bit) CMOS EPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AMD-K5-PR100ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR120ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR166ABX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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