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參數資料
| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
| 中文描述： | 32位卓越的價格/性能值微處理器（32位高性/價比微處理器） |
| 文件頁數： | 17/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
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18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
unit can operate independently, other units can continue exe-
cution when one or more units are stalled. A 16-entry reorder
buffer keeps track of the original instruction sequence and
ensures that the results are retired in program order.
4.3
Register Renaming
The x86 architecture has only eight general-purpose registers.
This significantly increases register reuse (loads and stores)
and register dependencies. The register reuse is addressed
with multiple load/store execution units and a dual-ported data
cache. The AMD-K5 processor uses register renaming to over-
come register dependencies. Multiple logical registers for each
physical register allow execution units to use the same physi-
cal name registers simultaneously.
4.4
64-Bit Data Bus Interface Unit
The AMD-K5 processor uses a 64-bit data bus that provides
higher throughput and support for 64-bit data paths, and a
cache/burst-oriented line refill for loading the processor’s
internal separate instruction and data caches. As code and
data enter the bus interface unit, the internal cache refills con-
tinually as fast as five clock cycles per cache line. The
enhanced bandwidth of the processor’s data bus and the con-
tinuous cache refill process reduces processing delays and sup-
ports superior processor and overall system performance.
4.5
Innovative x86 Instruction Predecoding
While processing variable-length instructions is manageable in
single-issue 4th-generation and dual-issue 5th-generation
CPUs, only the AMD-K5 processor employs the necessary inno-
vative techniques to issue as many as four x86 instructions per
clock cycle.
Every byte of code that enters the AMD-K5 processor is tagged
with associated predecode information that identifies the x86
instruction boundaries and enables multiple x86 instructions
(varying in length from 8 to 120 bits) to be aligned. Once
aligned, the instructions are assigned issue positions for the
most efficient instruction processing
contributing to the pro-
相關PDF資料 |
PDF描述 |
|---|---|
| AMD-K6-2 | 32 Bit Microprocessor With 64-Kbyte Level-one Cache High-Performance and Multimedia Execution Unit(帶64K字節(jié)緩存和高性能多媒體執(zhí)行單元的32位微處理器) |
| AMD-K6-III | 32-Bit Microprocessor Advanced RISC86 Superscalar Microarchitecture and 3D Technology(32位微處理器帶3D技術和高級的RISC86超標量微體系結構) |
| AMD-K6 | Circular Connector; No. of Contacts:5; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:14-5 RoHS Compliant: No |
| AMD27C64-150PI | 64 Kilobit (8,192 x 8-Bit) CMOS EPROM |
| AMD27C64 | 64 Kilobit (8,192 x 8-Bit) CMOS EPROM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AMD-K5-PR100ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR120ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR166ABX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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