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| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
| 中文描述： | 32位卓越的價格/性能值微處理器（32位高性/價比微處理器） |
| 文件頁數(shù)： | 28/100頁 |
| 文件大小： | 2533K |
| 代理商： | AMD-K5 |
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18
AMD-K5 Processor Data Sheet
18522F/0—Jan1997
PRELIMINARY INFORMATION
D63–D0
Data Lines
The D63–D0 signals are the 64-bit data bus. These signals are
driven during the second and subsequent clocks of write
cycles, with valid bytes indicated by BE7–BE0. They are sam-
pled when the BRDY signal is asserted for read cycles. (See
Switching Characteristics t
34
and t
35
.)
Input/Output
DP7–DP0
Data Parity
The DP7–DP0 signals provide even parity, one for each of the
eight bytes of the data bus. The eight data parity signals corre-
spond to the eight bytes of the data bus as follows:
Input/Output
These signals are driven with the data bus. Read cycles that do
not provide even parity when the read data is driven result in
the assertion of PCHK. Byte enables are negated for invalid
data bytes. For systems that do not use parity, DP7–DP0 should
be connected to V
CC
through a pull-up resistor. (See PCHK and
Switching Characteristics t
34
and
t
35
.)
EADS
Valid External Address
The EADS signal indicates that a valid address is driven on the
address bus during inquire cycles. EADS has an internal pull-
up resistor. (See Switching Characteristics t
16a
and
t
17
.)
Input
EWBE
External Write Buffer Empty
External system logic notifies the processor of pending buff-
ered write cycles by negating the EWBE signal. The processor
will hold writes to exclusive or modified cache lines until
EWBE is asserted.
Input
FERR
Floating-Point Error
The FERR signal is asserted as a result of an unmasked float-
ing-point error. It is only floated during test.
Output
I
DP7: D63–D56
DP6: D55–D48
DP5: D47–D40
DP4: D39–D32
I
DP3: D31–D24
DP2: D23–D16
DP1: D15–D8
DP0: D7–D0
I
I
I
I
I
I
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相關(guān)代理商/技術(shù)參數(shù) |
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| AMD-K5-PR100ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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