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參數(shù)資料
| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
| 中文描述： | 32位卓越的價格/性能值微處理器（32位高性/價比微處理器） |
| 文件頁數(shù)： | 16/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
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6
AMD-K5 Processor Data Sheet
18522F/0—Jan1997
PRELIMINARY INFORMATION
4
Architectural Introduction
The x86 architecture is the dominant standard for the personal
computer marketplace. However, maintaining backwards com-
patibility with previous generations of x86 processors carries
several inherent limitations associated with the x86 architec-
ture: variable-length instruction set, fewer general-purpose
registers, and complex addressing modes. The AMD-K5 proces-
sor overcomes these burdens by providing superscalar archi-
tecture that incorporates innovative technology: instruction
predecoding, improved cache architecture, branch prediction
with speculative execution, a superscalar RISC core, out-of-
order execution, and register renaming.
4.1
Superscalar RISC Core
The AMD-K5 processor’s superscalar RISC core consists of six
execution units: two arithmetic logic units (ALU), two load/
store units, one branch unit, and one floating-point unit (FPU).
This superscalar core is fully decoupled from the x86 bus
through the conversion of variable-length x86 instructions into
simple, fixed-length RISC operations (ROPs) that are easier to
handle and execute faster. Once the x86 instruction has been
converted, a dispatcher issues four ROPs at a time to the
superscalar core. The processor’s superscalar core can execute
at a peak rate of six ROPs per cycle. The superscalar core sup-
ports data forwarding and data bypassing to immediately for-
ward the results of an execution to successive instructions.
This eliminates the delay of writing the results to output regis-
ters or memory and reading them back to the instruction need-
ing the results.
4.2
Out-of-Order Execution
The AMD-K5 processor implements out-of-order execution to
eliminate delays due to pipeline dependencies. Each execution
unit has two reservation stations that hold ROPs prior to exe-
cution (except the FPU, which has one reservation station).
ROPs can be issued out of order from the reservation stations
and executed out of order. Some execution units will empty
their reservation stations before others. Since each execution
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| AMD-K6-2 | 32 Bit Microprocessor With 64-Kbyte Level-one Cache High-Performance and Multimedia Execution Unit(帶64K字節(jié)緩存和高性能多媒體執(zhí)行單元的32位微處理器) |
| AMD-K6-III | 32-Bit Microprocessor Advanced RISC86 Superscalar Microarchitecture and 3D Technology(32位微處理器帶3D技術(shù)和高級的RISC86超標(biāo)量微體系結(jié)構(gòu)) |
| AMD-K6 | Circular Connector; No. of Contacts:5; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:14-5 RoHS Compliant: No |
| AMD27C64-150PI | 64 Kilobit (8,192 x 8-Bit) CMOS EPROM |
| AMD27C64 | 64 Kilobit (8,192 x 8-Bit) CMOS EPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AMD-K5-PR100ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR120ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR133ABR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| AMD-K5-PR166ABX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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