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參數(shù)資料
| 型號： | AMD-K5 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
| 中文描述： | 32位卓越的價格/性能值微處理器（32位高性/價比微處理器） |
| 文件頁數(shù)： | 49/100頁 |
| 文件大?。?/td> | 2533K |
| 代理商： | AMD-K5 |
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39
18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
Single Transfer
Cycles
Single transfer cycles are initiated with the assertion of ADS
while negating the cache signal. The cycle is completed when
the BRDY signal is asserted by the external system. A single
transfer cycle requires a minimum of two external clock cycles.
Timing for a single write transfer cycle is illustrated in Figure
5. (See Figures 28, 29, 30, and 31 beginning on page 74.)
Figure 5. Single Writes (Zero Wait States)
Burst Read Cycles
The size of a burst read access is always 32 bytes sent as four
64-bit transfers. A burst read access is indicated by the asser-
tion of the CACHE signal, but if the external memory system
subsequently does not assert KEN, the access will be converted
to a single access. Data is sampled during the same clock that
BRDY is asserted. Wait states can be added by negating BRDY.
The initial address and the byte enables are not changed after
the initial access of a burst. External hardware must be config-
ured to determine the subsequent addresses of the burst in
accordance with the ordering specified in Table 11. PCHK is
driven two clocks following an associated data transfer to the
processor to indicate a data parity error. (See Figure 31 on
page 75 and Figure 32 on page 76.)
Burst Write Cycles
Like a burst read access, a burst write access is indicated by
the assertion of the CACHE pin. Burst write cycles (an exam-
ple of which is given in Figure 6) only occur for writebacks of
modified lines in the processor data cache. These transfers are
always four accesses. The address order for writeback cycles is
always 0, 8, 10, 18. All other accesses, including unaligned
accesses that cross 64-bit aligned boundaries, are sent as single
accesses or a series of single accesses. Negating BRDY until
CLK
ADS
BRDY
Data
Add/
W/R
Control
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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