參數(shù)資料
型號: AMD-K5
廠商: Advanced Micro Devices, Inc.
英文描述: 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器)
中文描述: 32位卓越的價格/性能值微處理器(32位高性/價比微處理器)
文件頁數(shù): 35/100頁
文件大?。?/td> 2533K
代理商: AMD-K5
25
18522F/0—Jan1997
AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
CLK
EADS
EWBE
FLUSH
FRCMC
HOLD
Clock
PEN
RESET
R/S
SMI
STPCLK
WB/WT
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Note 4
Synchronous
Synchronous
Asynchronous
Asynchronous
Synchronous
Note 4
Note 2
Note 6
Table 2.
Output Pins
Name
A4–A3
ADS
ADSC
APCHK
BE7–BE0
BREQ
CACHE
D/C
FERR
HIT
HITM
Notes:
1. All outputs float during Tri-State test mode.
Floated At (Note 1)
Bus Hold, Address Hold, BOFF
Bus Hold, BOFF
Bus Hold, BOFF
Always Driven
Bus Hold, BOFF
Always Driven
Bus Hold, BOFF
Bus Hold, BOFF
Always Driven
Always Driven
Always Driven
Name
HLDA
IERR
LOCK
M/IO
PCD
PCHK
PRDY
PWT
SCYC
SMIACT
W/R
Floated At (Note 1)
Always Driven
Always Driven
Bus Hold, BOFF
Bus Hold, BOFF
Bus Hold, BOFF
Always Driven
Always Driven
Bus Hold, BOFF
LOCK not asserted, Bus Hold, BOFF
Always Driven
Bus Hold, BOFF
Table 1.
Input Pins (continued)
Name
Type
Note
Name
Type
Note
Notes:
1. A20M may change during RESET or during a serializing event like an I/O write. A state change at other times will result in incorrect
address generation on subsequent memory cycles.
2. BF and FRCMC are normally connected to V
CC
or V
SS
by a jumper. For correct operation, any change on these signals should be
followed by a RESET.
3. BUSCHK is sampled in every clock. Any asserted sample is remembered and takes effect on the same clock as the last BRDY.
4. These are sampled in the same clock as BRDY.
5. This is sampled in the same clock as EADS.
6. These are sampled with the first BRDY or NA and must meet setup to every clock
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